source: rtems/doc/user/intr.t @ 211cafba

4.104.114.95
Last change on this file since 211cafba was 211cafba, checked in by Joel Sherrill <joel.sherrill@…>, on 04/16/08 at 18:30:16

2008-04-16 Joel Sherrill <joel.sherrill@…>

  • user/bsp.t, user/conf.t, user/init.t, user/intr.t, user/overview.t, user/timer.t: Correct default values. Make it clear that confdefs.h calculates the memory required for you.
  • Property mode set to 100644
File size: 12.1 KB
Line 
1@c
2@c  COPYRIGHT (c) 1988-2008.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@chapter Interrupt Manager
10
11@section Introduction
12
13Any real-time executive must provide a mechanism for
14quick response to externally generated interrupts to satisfy the
15critical time constraints of the application.  The interrupt
16manager provides this mechanism for RTEMS.  This manager permits
17quick interrupt response times by providing the critical ability
18to alter task execution which allows a task to be preempted upon
19exit from an ISR.  The interrupt manager includes the following
20directive:
21
22@itemize @bullet
23@item @code{@value{DIRPREFIX}interrupt_catch} - Establish an ISR
24@item @code{@value{DIRPREFIX}interrupt_disable} - Disable Interrupts
25@item @code{@value{DIRPREFIX}interrupt_enable} - Enable Interrupts
26@item @code{@value{DIRPREFIX}interrupt_flash} - Flash Interrupt
27@item @code{@value{DIRPREFIX}interrupt_is_in_progress} - Is an ISR in Progress
28@end itemize
29
30@section Background
31
32@subsection Processing an Interrupt
33
34@cindex interrupt processing
35
36The interrupt manager allows the application to
37connect a function to a hardware interrupt vector.  When an
38interrupt occurs, the processor will automatically vector to
39RTEMS.  RTEMS saves and restores all registers which are not
40preserved by the normal @value{LANGUAGE} calling convention
41for the target
42processor and invokes the user's ISR.  The user's ISR is
43responsible for processing the interrupt, clearing the interrupt
44if necessary, and device specific manipulation.
45
46@findex rtems_vector_number
47
48The @code{@value{DIRPREFIX}interrupt_catch}
49directive connects a procedure to
50an interrupt vector.  The vector number is managed using
51the @code{@value{DIRPREFIX}vector_number} data type.
52
53The interrupt service routine is assumed
54to abide by these conventions and have a prototype similar to
55the following:
56
57@ifset is-C
58@findex rtems_isr
59
60@example
61rtems_isr user_isr(
62  rtems_vector_number vector
63);
64@end example
65@end ifset
66
67@ifset is-Ada
68@example
69NOT SUPPORTED FROM Ada BINDING
70@end example
71@end ifset
72
73The vector number argument is provided by RTEMS to
74allow the application to identify the interrupt source.  This
75could be used to allow a single routine to service interrupts
76from multiple instances of the same device.  For example, a
77single routine could service interrupts from multiple serial
78ports and use the vector number to identify which port requires
79servicing.
80
81To minimize the masking of lower or equal priority
82level interrupts, the ISR should perform the minimum actions
83required to service the interrupt.  Other non-essential actions
84should be handled by application tasks.  Once the user's ISR has
85completed, it returns control to the RTEMS interrupt manager
86which will perform task dispatching and restore the registers
87saved before the ISR was invoked.
88
89The RTEMS interrupt manager guarantees that proper
90task scheduling and dispatching are performed at the conclusion
91of an ISR.  A system call made by the ISR may have readied a
92task of higher priority than the interrupted task.  Therefore,
93when the ISR completes, the postponed dispatch processing must
94be performed.  No dispatch processing is performed as part of
95directives which have been invoked by an ISR.
96
97Applications must adhere to the following rule if
98proper task scheduling and dispatching is to be performed:
99
100@itemize @b{ }
101
102@item @b{The interrupt manager must be used for all ISRs which
103may be interrupted by the highest priority ISR which invokes an
104RTEMS directive.}
105
106@end itemize
107
108Consider a processor which allows a numerically low
109interrupt level to interrupt a numerically greater interrupt
110level.  In this example, if an RTEMS directive is used in a
111level 4 ISR, then all ISRs which execute at levels 0 through 4
112must use the interrupt manager.
113
114Interrupts are nested whenever an interrupt occurs
115during the execution of another ISR.  RTEMS supports efficient
116interrupt nesting by allowing the nested ISRs to terminate
117without performing any dispatch processing.  Only when the
118outermost ISR terminates will the postponed dispatching occur.
119
120@subsection RTEMS Interrupt Levels
121
122@cindex interrupt levels
123
124Many processors support multiple interrupt levels or
125priorities.  The exact number of interrupt levels is processor
126dependent.  RTEMS internally supports 256 interrupt levels which
127are mapped to the processor's interrupt levels.  For specific
128information on the mapping between RTEMS and the target
129processor's interrupt levels, refer to the Interrupt Processing
130chapter of the Applications Supplement document for a specific
131target processor.
132
133@subsection Disabling of Interrupts by RTEMS
134
135@cindex disabling interrupts
136
137During the execution of directive calls, critical
138sections of code may be executed.  When these sections are
139encountered, RTEMS disables all maskable interrupts before the
140execution of the section and restores them to the previous level
141upon completion of the section.  RTEMS has been optimized to
142ensure that interrupts are disabled for a minimum length of
143time.  The maximum length of time interrupts are disabled by
144RTEMS is processor dependent and is detailed in the Timing
145Specification chapter of the Applications Supplement document
146for a specific target processor.
147
148Non-maskable interrupts (NMI) cannot be disabled, and
149ISRs which execute at this level MUST NEVER issue RTEMS system
150calls.  If a directive is invoked, unpredictable results may
151occur due to the inability of RTEMS to protect its critical
152sections.  However, ISRs that make no system calls may safely
153execute as non-maskable interrupts.
154
155@section Operations
156
157@subsection Establishing an ISR
158
159The @code{@value{DIRPREFIX}interrupt_catch}
160directive establishes an ISR for
161the system.  The address of the ISR and its associated CPU
162vector number are specified to this directive.  This directive
163installs the RTEMS interrupt wrapper in the processor's
164Interrupt Vector Table and the address of the user's ISR in the
165RTEMS' Vector Table.  This directive returns the previous
166contents of the specified vector in the RTEMS' Vector Table.
167
168@subsection Directives Allowed from an ISR
169
170Using the interrupt manager ensures that RTEMS knows
171when a directive is being called from an ISR.  The ISR may then
172use system calls to synchronize itself with an application task.
173The synchronization may involve messages, events or signals
174being passed by the ISR to the desired task.  Directives invoked
175by an ISR must operate only on objects which reside on the local
176node.  The following is a list of RTEMS system calls that may be
177made from an ISR:
178
179@itemize @bullet
180@item Task Management
181
182@itemize -
183@item task_get_note, task_set_note, task_suspend, task_resume
184@end itemize
185
186@item Clock Management
187
188@itemize -
189@item clock_get, clock_tick
190@end itemize
191
192@item Message, Event, and Signal Management
193
194@itemize -
195@item message_queue_send, message_queue_urgent
196@item event_send
197@item signal_send
198@end itemize
199
200@item Semaphore Management
201
202@itemize -
203@item semaphore_release
204@end itemize
205
206@item Dual-Ported Memory Management
207
208@itemize -
209@item port_external_to_internal, port_internal_to_external
210@end itemize
211
212@item IO Management
213
214@itemize -
215@item io_initialize, io_open, io_close, io_read, io_write, io_control
216@end itemize
217
218@item Fatal Error Management
219
220@itemize -
221@item fatal_error_occurred
222@end itemize
223
224@item Multiprocessing
225
226@itemize -
227@item multiprocessing_announce
228@end itemize
229@end itemize
230
231@section Directives
232
233This section details the interrupt manager's
234directives.  A subsection is dedicated to each of this manager's
235directives and describes the calling sequence, related
236constants, usage, and status codes.
237
238@c
239@c
240@c
241@page
242@subsection INTERRUPT_CATCH - Establish an ISR
243
244@cindex establish an ISR
245@cindex install an ISR
246
247@subheading CALLING SEQUENCE:
248
249@ifset is-C
250@findex rtems_interrupt_catch
251@example
252rtems_status_code rtems_interrupt_catch(
253  rtems_isr_entry      new_isr_handler,
254  rtems_vector_number  vector,
255  rtems_isr_entry     *old_isr_handler
256);
257@end example
258@end ifset
259
260@ifset is-Ada
261@example
262NOT SUPPORTED FROM Ada BINDING
263@end example
264@end ifset
265
266@subheading DIRECTIVE STATUS CODES:
267@code{@value{RPREFIX}SUCCESSFUL} - ISR established successfully@*
268@code{@value{RPREFIX}INVALID_NUMBER} - illegal vector number@*
269@code{@value{RPREFIX}INVALID_ADDRESS} - illegal ISR entry point or invalid @code{old_isr_handler}
270
271@subheading DESCRIPTION:
272
273This directive establishes an interrupt service
274routine (ISR) for the specified interrupt vector number.  The
275@code{new_isr_handler} parameter specifies the entry point of the ISR.
276The entry point of the previous ISR for the specified vector is
277returned in @code{old_isr_handler}.
278
279To release an interrupt vector, pass the old handler's address obtained
280when the vector was first capture.
281
282@subheading NOTES:
283
284This directive will not cause the calling task to be preempted.
285
286@c
287@c
288@c
289@page
290@subsection INTERRUPT_DISABLE - Disable Interrupts
291
292@cindex disable interrupts
293
294@subheading CALLING SEQUENCE:
295
296@ifset is-C
297@findex rtems_interrupt_disable
298@example
299void rtems_interrupt_disable(
300  rtems_interrupt_level  level
301);
302
303/* this is implemented as a macro and sets level as a side-effect */
304@end example
305@end ifset
306
307@ifset is-Ada
308@example
309function Interrupt_Disable return RTEMS.ISR_Level;
310@end example
311@end ifset
312
313@subheading DIRECTIVE STATUS CODES:
314
315NONE
316
317@subheading DESCRIPTION:
318
319This directive disables all maskable interrupts and returns
320the previous @code{level}.  A later invocation of the
321@code{@value{DIRPREFIX}interrupt_enable} directive should be used to
322restore the interrupt level.
323
324@subheading NOTES:
325
326This directive will not cause the calling task to be preempted.
327
328@ifset is-C
329@b{This directive is implemented as a macro which modifies the @code{level}
330parameter.}
331@end ifset
332
333@c
334@c
335@c
336@page
337@subsection INTERRUPT_ENABLE - Enable Interrupts
338
339@cindex enable interrupts
340
341@subheading CALLING SEQUENCE:
342
343@ifset is-C
344@findex rtems_interrupt_enable
345@example
346void rtems_interrupt_enable(
347  rtems_interrupt_level  level
348);
349@end example
350@end ifset
351
352@ifset is-Ada
353@example
354procedure Interrupt_Enable (
355   Level : in     RTEMS.ISR_Level
356);
357@end example
358@end ifset
359
360@subheading DIRECTIVE STATUS CODES:
361
362NONE
363
364@subheading DESCRIPTION:
365
366This directive enables maskable interrupts to the @code{level}
367which was returned by a previous call to
368@code{@value{DIRPREFIX}interrupt_disable}.
369Immediately prior to invoking this directive, maskable interrupts should
370be disabled by a call to @code{@value{DIRPREFIX}interrupt_disable}
371and will be enabled when this directive returns to the caller.
372
373@subheading NOTES:
374
375This directive will not cause the calling task to be preempted.
376
377
378@c
379@c
380@c
381@page
382@subsection INTERRUPT_FLASH - Flash Interrupts
383
384@cindex flash interrupts
385
386@subheading CALLING SEQUENCE:
387
388@ifset is-C
389@findex rtems_interrupt_flash
390@example
391void rtems_interrupt_flash(
392  rtems_interrupt_level level
393);
394@end example
395@end ifset
396
397@ifset is-Ada
398@example
399procedure Interrupt_Flash (
400   Level : in     RTEMS.ISR_Level
401);
402@end example
403@end ifset
404
405@subheading DIRECTIVE STATUS CODES:
406
407NONE
408
409@subheading DESCRIPTION:
410
411This directive temporarily enables maskable interrupts to the @code{level}
412which was returned by a previous call to
413@code{@value{DIRPREFIX}interrupt_disable}. 
414Immediately prior to invoking this directive, maskable interrupts should
415be disabled by a call to @code{@value{DIRPREFIX}interrupt_disable}
416and will be redisabled when this directive returns to the caller.
417
418@subheading NOTES:
419
420This directive will not cause the calling task to be preempted.
421
422@c
423@c
424@c
425@page
426@subsection INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress
427
428@cindex is interrupt in progress
429
430@subheading CALLING SEQUENCE:
431
432@ifset is-C
433@findex rtems_interrupt_is_in_progress
434@example
435rtems_boolean rtems_interrupt_is_in_progress( void );
436@end example
437@end ifset
438
439@ifset is-Ada
440@example
441function Interrupt_Is_In_Progress return RTEMS.Boolean;
442@end example
443@end ifset
444
445@subheading DIRECTIVE STATUS CODES:
446
447NONE
448
449@subheading DESCRIPTION:
450
451This directive returns @code{TRUE} if the processor is currently
452servicing an interrupt and @code{FALSE} otherwise.  A return value
453of @code{TRUE} indicates that the caller is an interrupt service
454routine, @b{NOT} a task.  The directives available to an interrupt
455service routine are restricted.
456
457@subheading NOTES:
458
459This directive will not cause the calling task to be preempted.
460
Note: See TracBrowser for help on using the repository browser.