source: rtems/doc/user/intr.t @ 1be10249

4.104.114.95
Last change on this file since 1be10249 was 1be10249, checked in by Joel Sherrill <joel.sherrill@…>, on 08/04/08 at 19:09:28

2008-08-04 Joel Sherrill <joel.sherrill@…>

PR 1288/doc

  • user/intr.t: Update callable from ISR section.
  • Property mode set to 100644
File size: 12.8 KB
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1@c
2@c  COPYRIGHT (c) 1988-2008.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@chapter Interrupt Manager
10
11@section Introduction
12
13Any real-time executive must provide a mechanism for
14quick response to externally generated interrupts to satisfy the
15critical time constraints of the application.  The interrupt
16manager provides this mechanism for RTEMS.  This manager permits
17quick interrupt response times by providing the critical ability
18to alter task execution which allows a task to be preempted upon
19exit from an ISR.  The interrupt manager includes the following
20directive:
21
22@itemize @bullet
23@item @code{@value{DIRPREFIX}interrupt_catch} - Establish an ISR
24@item @code{@value{DIRPREFIX}interrupt_disable} - Disable Interrupts
25@item @code{@value{DIRPREFIX}interrupt_enable} - Enable Interrupts
26@item @code{@value{DIRPREFIX}interrupt_flash} - Flash Interrupt
27@item @code{@value{DIRPREFIX}interrupt_is_in_progress} - Is an ISR in Progress
28@end itemize
29
30@section Background
31
32@subsection Processing an Interrupt
33
34@cindex interrupt processing
35
36The interrupt manager allows the application to
37connect a function to a hardware interrupt vector.  When an
38interrupt occurs, the processor will automatically vector to
39RTEMS.  RTEMS saves and restores all registers which are not
40preserved by the normal @value{LANGUAGE} calling convention
41for the target
42processor and invokes the user's ISR.  The user's ISR is
43responsible for processing the interrupt, clearing the interrupt
44if necessary, and device specific manipulation.
45
46@findex rtems_vector_number
47
48The @code{@value{DIRPREFIX}interrupt_catch}
49directive connects a procedure to
50an interrupt vector.  The vector number is managed using
51the @code{@value{DIRPREFIX}vector_number} data type.
52
53The interrupt service routine is assumed
54to abide by these conventions and have a prototype similar to
55the following:
56
57@ifset is-C
58@findex rtems_isr
59
60@example
61rtems_isr user_isr(
62  rtems_vector_number vector
63);
64@end example
65@end ifset
66
67@ifset is-Ada
68@example
69NOT SUPPORTED FROM Ada BINDING
70@end example
71@end ifset
72
73The vector number argument is provided by RTEMS to
74allow the application to identify the interrupt source.  This
75could be used to allow a single routine to service interrupts
76from multiple instances of the same device.  For example, a
77single routine could service interrupts from multiple serial
78ports and use the vector number to identify which port requires
79servicing.
80
81To minimize the masking of lower or equal priority
82level interrupts, the ISR should perform the minimum actions
83required to service the interrupt.  Other non-essential actions
84should be handled by application tasks.  Once the user's ISR has
85completed, it returns control to the RTEMS interrupt manager
86which will perform task dispatching and restore the registers
87saved before the ISR was invoked.
88
89The RTEMS interrupt manager guarantees that proper
90task scheduling and dispatching are performed at the conclusion
91of an ISR.  A system call made by the ISR may have readied a
92task of higher priority than the interrupted task.  Therefore,
93when the ISR completes, the postponed dispatch processing must
94be performed.  No dispatch processing is performed as part of
95directives which have been invoked by an ISR.
96
97Applications must adhere to the following rule if
98proper task scheduling and dispatching is to be performed:
99
100@itemize @b{ }
101
102@item @b{The interrupt manager must be used for all ISRs which
103may be interrupted by the highest priority ISR which invokes an
104RTEMS directive.}
105
106@end itemize
107
108Consider a processor which allows a numerically low
109interrupt level to interrupt a numerically greater interrupt
110level.  In this example, if an RTEMS directive is used in a
111level 4 ISR, then all ISRs which execute at levels 0 through 4
112must use the interrupt manager.
113
114Interrupts are nested whenever an interrupt occurs
115during the execution of another ISR.  RTEMS supports efficient
116interrupt nesting by allowing the nested ISRs to terminate
117without performing any dispatch processing.  Only when the
118outermost ISR terminates will the postponed dispatching occur.
119
120@subsection RTEMS Interrupt Levels
121
122@cindex interrupt levels
123
124Many processors support multiple interrupt levels or
125priorities.  The exact number of interrupt levels is processor
126dependent.  RTEMS internally supports 256 interrupt levels which
127are mapped to the processor's interrupt levels.  For specific
128information on the mapping between RTEMS and the target
129processor's interrupt levels, refer to the Interrupt Processing
130chapter of the Applications Supplement document for a specific
131target processor.
132
133@subsection Disabling of Interrupts by RTEMS
134
135@cindex disabling interrupts
136
137During the execution of directive calls, critical
138sections of code may be executed.  When these sections are
139encountered, RTEMS disables all maskable interrupts before the
140execution of the section and restores them to the previous level
141upon completion of the section.  RTEMS has been optimized to
142ensure that interrupts are disabled for a minimum length of
143time.  The maximum length of time interrupts are disabled by
144RTEMS is processor dependent and is detailed in the Timing
145Specification chapter of the Applications Supplement document
146for a specific target processor.
147
148Non-maskable interrupts (NMI) cannot be disabled, and
149ISRs which execute at this level MUST NEVER issue RTEMS system
150calls.  If a directive is invoked, unpredictable results may
151occur due to the inability of RTEMS to protect its critical
152sections.  However, ISRs that make no system calls may safely
153execute as non-maskable interrupts.
154
155@section Operations
156
157@subsection Establishing an ISR
158
159The @code{@value{DIRPREFIX}interrupt_catch}
160directive establishes an ISR for
161the system.  The address of the ISR and its associated CPU
162vector number are specified to this directive.  This directive
163installs the RTEMS interrupt wrapper in the processor's
164Interrupt Vector Table and the address of the user's ISR in the
165RTEMS' Vector Table.  This directive returns the previous
166contents of the specified vector in the RTEMS' Vector Table.
167
168@subsection Directives Allowed from an ISR
169
170Using the interrupt manager ensures that RTEMS knows
171when a directive is being called from an ISR.  The ISR may then
172use system calls to synchronize itself with an application task.
173The synchronization may involve messages, events or signals
174being passed by the ISR to the desired task.  Directives invoked
175by an ISR must operate only on objects which reside on the local
176node.  The following is a list of RTEMS system calls that may be
177made from an ISR:
178
179@itemize @bullet
180@item Task Management
181
182Although it is acceptable to operate on the RTEMS_SELF task (e.g.
183the currently executing task), while in an ISR, this will refer
184to the interrupted task.  Most of the time, it is an application
185implementation error to use RTEMS_SELF from an ISR.
186
187@itemize -
188@item rtems_task_get_note, rtems_task_set_note, rtems_task_suspend, rtems_task_resume
189@end itemize
190
191@item Clock and Timer Management
192
193@itemize -
194@item rtems_clock_get, rtems_clock_tick
195@item rtems_timer_fire_after, rtems_timer_fire_when, rtems_timer_cancel
196@end itemize
197
198@item Message, Event, and Signal Management
199
200@itemize -
201@item rtems_message_queue_send, rtems_message_queue_urgent
202@item rtems_event_send
203@item rtems_signal_send
204@end itemize
205
206@item Semaphore Management
207
208@itemize -
209@item rtems_semaphore_release
210@end itemize
211
212@item Dual-Ported Memory Management
213
214@itemize -
215@item rtems_port_external_to_internal, rtems_port_internal_to_external
216@end itemize
217
218@item IO Management
219
220The following services are safe to call from an ISR if and only if
221the device driver service invoked is also safe.  The IO Manager itself
222is safe but the invoked driver entry point may or may not be.
223@itemize -
224@item rtems_io_initialize, rtems_io_open, rtems_io_close, rtems_io_read, rtems_io_write, rtems_io_control
225@end itemize
226
227@item Fatal Error Management
228
229@itemize -
230@item rtems_fatal_error_occurred
231@end itemize
232
233@item Multiprocessing
234
235@itemize -
236@item rtems_multiprocessing_announce
237@end itemize
238@end itemize
239
240@section Directives
241
242This section details the interrupt manager's
243directives.  A subsection is dedicated to each of this manager's
244directives and describes the calling sequence, related
245constants, usage, and status codes.
246
247@c
248@c
249@c
250@page
251@subsection INTERRUPT_CATCH - Establish an ISR
252
253@cindex establish an ISR
254@cindex install an ISR
255
256@subheading CALLING SEQUENCE:
257
258@ifset is-C
259@findex rtems_interrupt_catch
260@example
261rtems_status_code rtems_interrupt_catch(
262  rtems_isr_entry      new_isr_handler,
263  rtems_vector_number  vector,
264  rtems_isr_entry     *old_isr_handler
265);
266@end example
267@end ifset
268
269@ifset is-Ada
270@example
271NOT SUPPORTED FROM Ada BINDING
272@end example
273@end ifset
274
275@subheading DIRECTIVE STATUS CODES:
276@code{@value{RPREFIX}SUCCESSFUL} - ISR established successfully@*
277@code{@value{RPREFIX}INVALID_NUMBER} - illegal vector number@*
278@code{@value{RPREFIX}INVALID_ADDRESS} - illegal ISR entry point or invalid @code{old_isr_handler}
279
280@subheading DESCRIPTION:
281
282This directive establishes an interrupt service
283routine (ISR) for the specified interrupt vector number.  The
284@code{new_isr_handler} parameter specifies the entry point of the ISR.
285The entry point of the previous ISR for the specified vector is
286returned in @code{old_isr_handler}.
287
288To release an interrupt vector, pass the old handler's address obtained
289when the vector was first capture.
290
291@subheading NOTES:
292
293This directive will not cause the calling task to be preempted.
294
295@c
296@c
297@c
298@page
299@subsection INTERRUPT_DISABLE - Disable Interrupts
300
301@cindex disable interrupts
302
303@subheading CALLING SEQUENCE:
304
305@ifset is-C
306@findex rtems_interrupt_disable
307@example
308void rtems_interrupt_disable(
309  rtems_interrupt_level  level
310);
311
312/* this is implemented as a macro and sets level as a side-effect */
313@end example
314@end ifset
315
316@ifset is-Ada
317@example
318function Interrupt_Disable return RTEMS.ISR_Level;
319@end example
320@end ifset
321
322@subheading DIRECTIVE STATUS CODES:
323
324NONE
325
326@subheading DESCRIPTION:
327
328This directive disables all maskable interrupts and returns
329the previous @code{level}.  A later invocation of the
330@code{@value{DIRPREFIX}interrupt_enable} directive should be used to
331restore the interrupt level.
332
333@subheading NOTES:
334
335This directive will not cause the calling task to be preempted.
336
337@ifset is-C
338@b{This directive is implemented as a macro which modifies the @code{level}
339parameter.}
340@end ifset
341
342@c
343@c
344@c
345@page
346@subsection INTERRUPT_ENABLE - Enable Interrupts
347
348@cindex enable interrupts
349
350@subheading CALLING SEQUENCE:
351
352@ifset is-C
353@findex rtems_interrupt_enable
354@example
355void rtems_interrupt_enable(
356  rtems_interrupt_level  level
357);
358@end example
359@end ifset
360
361@ifset is-Ada
362@example
363procedure Interrupt_Enable (
364   Level : in     RTEMS.ISR_Level
365);
366@end example
367@end ifset
368
369@subheading DIRECTIVE STATUS CODES:
370
371NONE
372
373@subheading DESCRIPTION:
374
375This directive enables maskable interrupts to the @code{level}
376which was returned by a previous call to
377@code{@value{DIRPREFIX}interrupt_disable}.
378Immediately prior to invoking this directive, maskable interrupts should
379be disabled by a call to @code{@value{DIRPREFIX}interrupt_disable}
380and will be enabled when this directive returns to the caller.
381
382@subheading NOTES:
383
384This directive will not cause the calling task to be preempted.
385
386
387@c
388@c
389@c
390@page
391@subsection INTERRUPT_FLASH - Flash Interrupts
392
393@cindex flash interrupts
394
395@subheading CALLING SEQUENCE:
396
397@ifset is-C
398@findex rtems_interrupt_flash
399@example
400void rtems_interrupt_flash(
401  rtems_interrupt_level level
402);
403@end example
404@end ifset
405
406@ifset is-Ada
407@example
408procedure Interrupt_Flash (
409   Level : in     RTEMS.ISR_Level
410);
411@end example
412@end ifset
413
414@subheading DIRECTIVE STATUS CODES:
415
416NONE
417
418@subheading DESCRIPTION:
419
420This directive temporarily enables maskable interrupts to the @code{level}
421which was returned by a previous call to
422@code{@value{DIRPREFIX}interrupt_disable}. 
423Immediately prior to invoking this directive, maskable interrupts should
424be disabled by a call to @code{@value{DIRPREFIX}interrupt_disable}
425and will be redisabled when this directive returns to the caller.
426
427@subheading NOTES:
428
429This directive will not cause the calling task to be preempted.
430
431@c
432@c
433@c
434@page
435@subsection INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress
436
437@cindex is interrupt in progress
438
439@subheading CALLING SEQUENCE:
440
441@ifset is-C
442@findex rtems_interrupt_is_in_progress
443@example
444rtems_boolean rtems_interrupt_is_in_progress( void );
445@end example
446@end ifset
447
448@ifset is-Ada
449@example
450function Interrupt_Is_In_Progress return RTEMS.Boolean;
451@end example
452@end ifset
453
454@subheading DIRECTIVE STATUS CODES:
455
456NONE
457
458@subheading DESCRIPTION:
459
460This directive returns @code{TRUE} if the processor is currently
461servicing an interrupt and @code{FALSE} otherwise.  A return value
462of @code{TRUE} indicates that the caller is an interrupt service
463routine, @b{NOT} a task.  The directives available to an interrupt
464service routine are restricted.
465
466@subheading NOTES:
467
468This directive will not cause the calling task to be preempted.
469
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