source: rtems/doc/user/intr.t @ 108a2e74

4.9
Last change on this file since 108a2e74 was 108a2e74, checked in by Joel Sherrill <joel.sherrill@…>, on 02/27/09 at 16:02:34

2009-02-27 Joel Sherrill <joel.sherrill@…>

PR 1387/doc

  • user/intr.t: Add Interrupt Manager services to list of services callable from ISR.
  • Property mode set to 100644
File size: 12.9 KB
Line 
1@c
2@c  COPYRIGHT (c) 1988-2008.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@chapter Interrupt Manager
10
11@section Introduction
12
13Any real-time executive must provide a mechanism for
14quick response to externally generated interrupts to satisfy the
15critical time constraints of the application.  The interrupt
16manager provides this mechanism for RTEMS.  This manager permits
17quick interrupt response times by providing the critical ability
18to alter task execution which allows a task to be preempted upon
19exit from an ISR.  The interrupt manager includes the following
20directive:
21
22@itemize @bullet
23@item @code{@value{DIRPREFIX}interrupt_catch} - Establish an ISR
24@item @code{@value{DIRPREFIX}interrupt_disable} - Disable Interrupts
25@item @code{@value{DIRPREFIX}interrupt_enable} - Enable Interrupts
26@item @code{@value{DIRPREFIX}interrupt_flash} - Flash Interrupt
27@item @code{@value{DIRPREFIX}interrupt_is_in_progress} - Is an ISR in Progress
28@end itemize
29
30@section Background
31
32@subsection Processing an Interrupt
33
34@cindex interrupt processing
35
36The interrupt manager allows the application to
37connect a function to a hardware interrupt vector.  When an
38interrupt occurs, the processor will automatically vector to
39RTEMS.  RTEMS saves and restores all registers which are not
40preserved by the normal @value{LANGUAGE} calling convention
41for the target
42processor and invokes the user's ISR.  The user's ISR is
43responsible for processing the interrupt, clearing the interrupt
44if necessary, and device specific manipulation.
45
46@findex rtems_vector_number
47
48The @code{@value{DIRPREFIX}interrupt_catch}
49directive connects a procedure to
50an interrupt vector.  The vector number is managed using
51the @code{@value{DIRPREFIX}vector_number} data type.
52
53The interrupt service routine is assumed
54to abide by these conventions and have a prototype similar to
55the following:
56
57@ifset is-C
58@findex rtems_isr
59
60@example
61rtems_isr user_isr(
62  rtems_vector_number vector
63);
64@end example
65@end ifset
66
67@ifset is-Ada
68@example
69NOT SUPPORTED FROM Ada BINDING
70@end example
71@end ifset
72
73The vector number argument is provided by RTEMS to
74allow the application to identify the interrupt source.  This
75could be used to allow a single routine to service interrupts
76from multiple instances of the same device.  For example, a
77single routine could service interrupts from multiple serial
78ports and use the vector number to identify which port requires
79servicing.
80
81To minimize the masking of lower or equal priority
82level interrupts, the ISR should perform the minimum actions
83required to service the interrupt.  Other non-essential actions
84should be handled by application tasks.  Once the user's ISR has
85completed, it returns control to the RTEMS interrupt manager
86which will perform task dispatching and restore the registers
87saved before the ISR was invoked.
88
89The RTEMS interrupt manager guarantees that proper
90task scheduling and dispatching are performed at the conclusion
91of an ISR.  A system call made by the ISR may have readied a
92task of higher priority than the interrupted task.  Therefore,
93when the ISR completes, the postponed dispatch processing must
94be performed.  No dispatch processing is performed as part of
95directives which have been invoked by an ISR.
96
97Applications must adhere to the following rule if
98proper task scheduling and dispatching is to be performed:
99
100@itemize @b{ }
101
102@item @b{The interrupt manager must be used for all ISRs which
103may be interrupted by the highest priority ISR which invokes an
104RTEMS directive.}
105
106@end itemize
107
108Consider a processor which allows a numerically low
109interrupt level to interrupt a numerically greater interrupt
110level.  In this example, if an RTEMS directive is used in a
111level 4 ISR, then all ISRs which execute at levels 0 through 4
112must use the interrupt manager.
113
114Interrupts are nested whenever an interrupt occurs
115during the execution of another ISR.  RTEMS supports efficient
116interrupt nesting by allowing the nested ISRs to terminate
117without performing any dispatch processing.  Only when the
118outermost ISR terminates will the postponed dispatching occur.
119
120@subsection RTEMS Interrupt Levels
121
122@cindex interrupt levels
123
124Many processors support multiple interrupt levels or
125priorities.  The exact number of interrupt levels is processor
126dependent.  RTEMS internally supports 256 interrupt levels which
127are mapped to the processor's interrupt levels.  For specific
128information on the mapping between RTEMS and the target
129processor's interrupt levels, refer to the Interrupt Processing
130chapter of the Applications Supplement document for a specific
131target processor.
132
133@subsection Disabling of Interrupts by RTEMS
134
135@cindex disabling interrupts
136
137During the execution of directive calls, critical
138sections of code may be executed.  When these sections are
139encountered, RTEMS disables all maskable interrupts before the
140execution of the section and restores them to the previous level
141upon completion of the section.  RTEMS has been optimized to
142ensure that interrupts are disabled for a minimum length of
143time.  The maximum length of time interrupts are disabled by
144RTEMS is processor dependent and is detailed in the Timing
145Specification chapter of the Applications Supplement document
146for a specific target processor.
147
148Non-maskable interrupts (NMI) cannot be disabled, and
149ISRs which execute at this level MUST NEVER issue RTEMS system
150calls.  If a directive is invoked, unpredictable results may
151occur due to the inability of RTEMS to protect its critical
152sections.  However, ISRs that make no system calls may safely
153execute as non-maskable interrupts.
154
155@section Operations
156
157@subsection Establishing an ISR
158
159The @code{@value{DIRPREFIX}interrupt_catch}
160directive establishes an ISR for
161the system.  The address of the ISR and its associated CPU
162vector number are specified to this directive.  This directive
163installs the RTEMS interrupt wrapper in the processor's
164Interrupt Vector Table and the address of the user's ISR in the
165RTEMS' Vector Table.  This directive returns the previous
166contents of the specified vector in the RTEMS' Vector Table.
167
168@subsection Directives Allowed from an ISR
169
170Using the interrupt manager ensures that RTEMS knows
171when a directive is being called from an ISR.  The ISR may then
172use system calls to synchronize itself with an application task.
173The synchronization may involve messages, events or signals
174being passed by the ISR to the desired task.  Directives invoked
175by an ISR must operate only on objects which reside on the local
176node.  The following is a list of RTEMS system calls that may be
177made from an ISR:
178
179@itemize @bullet
180@item Task Management
181
182Although it is acceptable to operate on the RTEMS_SELF task (e.g.
183the currently executing task), while in an ISR, this will refer
184to the interrupted task.  Most of the time, it is an application
185implementation error to use RTEMS_SELF from an ISR.
186
187@itemize -
188@item rtems_task_get_note
189@item rtems_task_set_note
190@item rtems_task_suspend
191@item rtems_task_resume
192@end itemize
193
194@item Interrupt Management
195
196@itemize -
197@item  rtems_interrupt_enable
198@item rtems_interrupt_disable
199@item rtems_interrupt_flash
200@item rtems_interrupt_is_in_progress
201@item rtems_interrupt_catch
202@end itemize
203
204@item Message, Event, and Signal Management
205
206@itemize -
207@item rtems_message_queue_send
208@item rtems_message_queue_urgent
209@item rtems_event_send
210@item rtems_signal_send
211@end itemize
212
213@item Semaphore Management
214
215@itemize -
216@item rtems_semaphore_release
217@end itemize
218
219@item Dual-Ported Memory Management
220
221@itemize -
222@item rtems_port_external_to_internal
223@item rtems_port_internal_to_external
224@end itemize
225
226@item IO Management
227
228The following services are safe to call from an ISR if and only if
229the device driver service invoked is also safe.  The IO Manager itself
230is safe but the invoked driver entry point may or may not be.
231@itemize -
232@item rtems_io_initialize
233@item rtems_io_open
234@item rtems_io_close
235@item rtems_io_read
236@item rtems_io_write
237@item rtems_io_control
238@end itemize
239
240@item Fatal Error Management
241
242@itemize -
243@item rtems_fatal_error_occurred
244@end itemize
245
246@item Multiprocessing
247
248@itemize -
249@item rtems_multiprocessing_announce
250@end itemize
251@end itemize
252
253@section Directives
254
255This section details the interrupt manager's
256directives.  A subsection is dedicated to each of this manager's
257directives and describes the calling sequence, related
258constants, usage, and status codes.
259
260@c
261@c
262@c
263@page
264@subsection INTERRUPT_CATCH - Establish an ISR
265
266@cindex establish an ISR
267@cindex install an ISR
268
269@subheading CALLING SEQUENCE:
270
271@ifset is-C
272@findex rtems_interrupt_catch
273@example
274rtems_status_code rtems_interrupt_catch(
275  rtems_isr_entry      new_isr_handler,
276  rtems_vector_number  vector,
277  rtems_isr_entry     *old_isr_handler
278);
279@end example
280@end ifset
281
282@ifset is-Ada
283@example
284NOT SUPPORTED FROM Ada BINDING
285@end example
286@end ifset
287
288@subheading DIRECTIVE STATUS CODES:
289@code{@value{RPREFIX}SUCCESSFUL} - ISR established successfully@*
290@code{@value{RPREFIX}INVALID_NUMBER} - illegal vector number@*
291@code{@value{RPREFIX}INVALID_ADDRESS} - illegal ISR entry point or invalid @code{old_isr_handler}
292
293@subheading DESCRIPTION:
294
295This directive establishes an interrupt service
296routine (ISR) for the specified interrupt vector number.  The
297@code{new_isr_handler} parameter specifies the entry point of the ISR.
298The entry point of the previous ISR for the specified vector is
299returned in @code{old_isr_handler}.
300
301To release an interrupt vector, pass the old handler's address obtained
302when the vector was first capture.
303
304@subheading NOTES:
305
306This directive will not cause the calling task to be preempted.
307
308@c
309@c
310@c
311@page
312@subsection INTERRUPT_DISABLE - Disable Interrupts
313
314@cindex disable interrupts
315
316@subheading CALLING SEQUENCE:
317
318@ifset is-C
319@findex rtems_interrupt_disable
320@example
321void rtems_interrupt_disable(
322  rtems_interrupt_level  level
323);
324
325/* this is implemented as a macro and sets level as a side-effect */
326@end example
327@end ifset
328
329@ifset is-Ada
330@example
331function Interrupt_Disable return RTEMS.ISR_Level;
332@end example
333@end ifset
334
335@subheading DIRECTIVE STATUS CODES:
336
337NONE
338
339@subheading DESCRIPTION:
340
341This directive disables all maskable interrupts and returns
342the previous @code{level}.  A later invocation of the
343@code{@value{DIRPREFIX}interrupt_enable} directive should be used to
344restore the interrupt level.
345
346@subheading NOTES:
347
348This directive will not cause the calling task to be preempted.
349
350@ifset is-C
351@b{This directive is implemented as a macro which modifies the @code{level}
352parameter.}
353@end ifset
354
355@c
356@c
357@c
358@page
359@subsection INTERRUPT_ENABLE - Enable Interrupts
360
361@cindex enable interrupts
362
363@subheading CALLING SEQUENCE:
364
365@ifset is-C
366@findex rtems_interrupt_enable
367@example
368void rtems_interrupt_enable(
369  rtems_interrupt_level  level
370);
371@end example
372@end ifset
373
374@ifset is-Ada
375@example
376procedure Interrupt_Enable (
377   Level : in     RTEMS.ISR_Level
378);
379@end example
380@end ifset
381
382@subheading DIRECTIVE STATUS CODES:
383
384NONE
385
386@subheading DESCRIPTION:
387
388This directive enables maskable interrupts to the @code{level}
389which was returned by a previous call to
390@code{@value{DIRPREFIX}interrupt_disable}.
391Immediately prior to invoking this directive, maskable interrupts should
392be disabled by a call to @code{@value{DIRPREFIX}interrupt_disable}
393and will be enabled when this directive returns to the caller.
394
395@subheading NOTES:
396
397This directive will not cause the calling task to be preempted.
398
399
400@c
401@c
402@c
403@page
404@subsection INTERRUPT_FLASH - Flash Interrupts
405
406@cindex flash interrupts
407
408@subheading CALLING SEQUENCE:
409
410@ifset is-C
411@findex rtems_interrupt_flash
412@example
413void rtems_interrupt_flash(
414  rtems_interrupt_level level
415);
416@end example
417@end ifset
418
419@ifset is-Ada
420@example
421procedure Interrupt_Flash (
422   Level : in     RTEMS.ISR_Level
423);
424@end example
425@end ifset
426
427@subheading DIRECTIVE STATUS CODES:
428
429NONE
430
431@subheading DESCRIPTION:
432
433This directive temporarily enables maskable interrupts to the @code{level}
434which was returned by a previous call to
435@code{@value{DIRPREFIX}interrupt_disable}. 
436Immediately prior to invoking this directive, maskable interrupts should
437be disabled by a call to @code{@value{DIRPREFIX}interrupt_disable}
438and will be redisabled when this directive returns to the caller.
439
440@subheading NOTES:
441
442This directive will not cause the calling task to be preempted.
443
444@c
445@c
446@c
447@page
448@subsection INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress
449
450@cindex is interrupt in progress
451
452@subheading CALLING SEQUENCE:
453
454@ifset is-C
455@findex rtems_interrupt_is_in_progress
456@example
457bool rtems_interrupt_is_in_progress( void );
458@end example
459@end ifset
460
461@ifset is-Ada
462@example
463function Interrupt_Is_In_Progress return RTEMS.Boolean;
464@end example
465@end ifset
466
467@subheading DIRECTIVE STATUS CODES:
468
469NONE
470
471@subheading DESCRIPTION:
472
473This directive returns @code{TRUE} if the processor is currently
474servicing an interrupt and @code{FALSE} otherwise.  A return value
475of @code{TRUE} indicates that the caller is an interrupt service
476routine, @b{NOT} a task.  The directives available to an interrupt
477service routine are restricted.
478
479@subheading NOTES:
480
481This directive will not cause the calling task to be preempted.
482
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