[ae68ff0] | 1 | @c |
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[1e524995] | 2 | @c COPYRIGHT (c) 1988-1998. |
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[ae68ff0] | 3 | @c On-Line Applications Research Corporation (OAR). |
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| 4 | @c All rights reserved. |
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| 5 | @c |
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[139b2e4a] | 6 | @c $Id$ |
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| 7 | @c |
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[ae68ff0] | 8 | |
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| 9 | @ifinfo |
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| 10 | @node Interrupt Manager, Interrupt Manager Introduction, TASK_WAKE_WHEN - Wake up when specified, Top |
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| 11 | @end ifinfo |
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| 12 | @chapter Interrupt Manager |
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| 13 | @ifinfo |
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| 14 | @menu |
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| 15 | * Interrupt Manager Introduction:: |
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| 16 | * Interrupt Manager Background:: |
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| 17 | * Interrupt Manager Operations:: |
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| 18 | * Interrupt Manager Directives:: |
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| 19 | @end menu |
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| 20 | @end ifinfo |
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| 21 | |
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| 22 | @ifinfo |
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| 23 | @node Interrupt Manager Introduction, Interrupt Manager Background, Interrupt Manager, Interrupt Manager |
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| 24 | @end ifinfo |
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| 25 | @section Introduction |
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| 26 | |
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| 27 | Any real-time executive must provide a mechanism for |
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| 28 | quick response to externally generated interrupts to satisfy the |
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| 29 | critical time constraints of the application. The interrupt |
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| 30 | manager provides this mechanism for RTEMS. This manager permits |
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| 31 | quick interrupt response times by providing the critical ability |
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| 32 | to alter task execution which allows a task to be preempted upon |
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| 33 | exit from an ISR. The interrupt manager includes the following |
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| 34 | directive: |
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| 35 | |
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| 36 | @itemize @bullet |
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| 37 | @item @code{interrupt_catch} - Establish an ISR |
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[7e8a1fc] | 38 | @item @code{interrupt_disable} - Disable Interrupts |
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| 39 | @item @code{interrupt_enable} - Enable Interrupts |
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| 40 | @item @code{interrupt_flash} - Flash Interrupt |
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| 41 | @item @code{interrupt_is_in_progress} - Is an ISR in Progress |
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[ae68ff0] | 42 | @end itemize |
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| 43 | |
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| 44 | @ifinfo |
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| 45 | @node Interrupt Manager Background, Processing an Interrupt, Interrupt Manager Introduction, Interrupt Manager |
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| 46 | @end ifinfo |
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| 47 | @section Background |
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| 48 | @ifinfo |
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| 49 | @menu |
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| 50 | * Processing an Interrupt:: |
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| 51 | * RTEMS Interrupt Levels:: |
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| 52 | * Disabling of Interrupts by RTEMS:: |
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| 53 | @end menu |
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| 54 | @end ifinfo |
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| 55 | |
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| 56 | @ifinfo |
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| 57 | @node Processing an Interrupt, RTEMS Interrupt Levels, Interrupt Manager Background, Interrupt Manager Background |
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| 58 | @end ifinfo |
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| 59 | @subsection Processing an Interrupt |
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| 60 | |
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| 61 | The interrupt manager allows the application to |
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| 62 | connect a function to a hardware interrupt vector. When an |
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| 63 | interrupt occurs, the processor will automatically vector to |
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| 64 | RTEMS. RTEMS saves and restores all registers which are not |
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[a94c5a5d] | 65 | preserved by the normal @value{LANGUAGE} calling convention |
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[61389eac] | 66 | for the target |
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[ae68ff0] | 67 | processor and invokes the user's ISR. The user's ISR is |
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| 68 | responsible for processing the interrupt, clearing the interrupt |
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| 69 | if necessary, and device specific manipulation. |
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| 70 | |
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| 71 | The interrupt_catch directive connects a procedure to |
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| 72 | an interrupt vector. The interrupt service routine is assumed |
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| 73 | to abide by these conventions and have a prototype similar to |
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| 74 | the following: |
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| 75 | |
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[61389eac] | 76 | @ifset is-C |
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[ae68ff0] | 77 | @example |
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| 78 | rtems_isr user_isr( |
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| 79 | rtems_vector_number vector |
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| 80 | ); |
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| 81 | @end example |
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[61389eac] | 82 | @end ifset |
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| 83 | |
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| 84 | @ifset is-Ada |
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| 85 | @example |
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| 86 | procedure User_ISR ( |
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| 87 | vector : in RTEMS.Vector_Number |
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| 88 | ); |
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| 89 | @end example |
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| 90 | @end ifset |
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[ae68ff0] | 91 | |
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| 92 | The vector number argument is provided by RTEMS to |
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| 93 | allow the application to identify the interrupt source. This |
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| 94 | could be used to allow a single routine to service interrupts |
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| 95 | from multiple instances of the same device. For example, a |
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| 96 | single routine could service interrupts from multiple serial |
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| 97 | ports and use the vector number to identify which port requires |
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| 98 | servicing. |
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| 99 | |
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| 100 | To minimize the masking of lower or equal priority |
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| 101 | level interrupts, the ISR should perform the minimum actions |
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| 102 | required to service the interrupt. Other non-essential actions |
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| 103 | should be handled by application tasks. Once the user's ISR has |
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| 104 | completed, it returns control to the RTEMS interrupt manager |
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| 105 | which will perform task dispatching and restore the registers |
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| 106 | saved before the ISR was invoked. |
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| 107 | |
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| 108 | The RTEMS interrupt manager guarantees that proper |
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| 109 | task scheduling and dispatching are performed at the conclusion |
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| 110 | of an ISR. A system call made by the ISR may have readied a |
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| 111 | task of higher priority than the interrupted task. Therefore, |
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| 112 | when the ISR completes, the postponed dispatch processing must |
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| 113 | be performed. No dispatch processing is performed as part of |
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| 114 | directives which have been invoked by an ISR. |
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| 115 | |
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| 116 | Applications must adhere to the following rule if |
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| 117 | proper task scheduling and dispatching is to be performed: |
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| 118 | |
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[61389eac] | 119 | @itemize @b{ } |
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[ae68ff0] | 120 | |
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| 121 | @item @b{The interrupt manager must be used for all ISRs which |
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| 122 | may be interrupted by the highest priority ISR which invokes an |
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| 123 | RTEMS directive.} |
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| 124 | |
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| 125 | @end itemize |
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| 126 | |
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| 127 | |
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| 128 | Consider a processor which allows a numerically low |
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| 129 | interrupt level to interrupt a numerically greater interrupt |
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| 130 | level. In this example, if an RTEMS directive is used in a |
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| 131 | level 4 ISR, then all ISRs which execute at levels 0 through 4 |
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| 132 | must use the interrupt manager. |
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| 133 | |
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| 134 | Interrupts are nested whenever an interrupt occurs |
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| 135 | during the execution of another ISR. RTEMS supports efficient |
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| 136 | interrupt nesting by allowing the nested ISRs to terminate |
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| 137 | without performing any dispatch processing. Only when the |
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| 138 | outermost ISR terminates will the postponed dispatching occur. |
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| 139 | |
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| 140 | @ifinfo |
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| 141 | @node RTEMS Interrupt Levels, Disabling of Interrupts by RTEMS, Processing an Interrupt, Interrupt Manager Background |
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| 142 | @end ifinfo |
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| 143 | @subsection RTEMS Interrupt Levels |
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| 144 | |
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| 145 | Many processors support multiple interrupt levels or |
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| 146 | priorities. The exact number of interrupt levels is processor |
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| 147 | dependent. RTEMS internally supports 256 interrupt levels which |
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| 148 | are mapped to the processor's interrupt levels. For specific |
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| 149 | information on the mapping between RTEMS and the target |
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| 150 | processor's interrupt levels, refer to the Interrupt Processing |
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[17a3c69] | 151 | chapter of the Applications Supplement document for a specific |
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[ae68ff0] | 152 | target processor. |
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| 153 | |
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| 154 | @ifinfo |
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| 155 | @node Disabling of Interrupts by RTEMS, Interrupt Manager Operations, RTEMS Interrupt Levels, Interrupt Manager Background |
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| 156 | @end ifinfo |
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| 157 | @subsection Disabling of Interrupts by RTEMS |
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| 158 | |
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| 159 | During the execution of directive calls, critical |
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| 160 | sections of code may be executed. When these sections are |
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| 161 | encountered, RTEMS disables all maskable interrupts before the |
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| 162 | execution of the section and restores them to the previous level |
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| 163 | upon completion of the section. RTEMS has been optimized to |
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| 164 | insure that interrupts are disabled for a minimum length of |
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| 165 | time. The maximum length of time interrupts are disabled by |
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| 166 | RTEMS is processor dependent and is detailed in the Timing |
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[17a3c69] | 167 | Specification chapter of the Applications Supplement document |
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[ae68ff0] | 168 | for a specific target processor. |
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| 169 | |
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| 170 | Non-maskable interrupts (NMI) cannot be disabled, and |
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| 171 | ISRs which execute at this level MUST NEVER issue RTEMS system |
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| 172 | calls. If a directive is invoked, unpredictable results may |
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| 173 | occur due to the inability of RTEMS to protect its critical |
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| 174 | sections. However, ISRs that make no system calls may safely |
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| 175 | execute as non-maskable interrupts. |
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| 176 | |
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| 177 | @ifinfo |
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| 178 | @node Interrupt Manager Operations, Establishing an ISR, Disabling of Interrupts by RTEMS, Interrupt Manager |
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| 179 | @end ifinfo |
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| 180 | @section Operations |
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| 181 | @ifinfo |
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| 182 | @menu |
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| 183 | * Establishing an ISR:: |
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| 184 | * Directives Allowed from an ISR:: |
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| 185 | @end menu |
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| 186 | @end ifinfo |
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| 187 | |
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| 188 | @ifinfo |
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| 189 | @node Establishing an ISR, Directives Allowed from an ISR, Interrupt Manager Operations, Interrupt Manager Operations |
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| 190 | @end ifinfo |
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| 191 | @subsection Establishing an ISR |
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| 192 | |
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| 193 | The interrupt_catch directive establishes an ISR for |
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| 194 | the system. The address of the ISR and its associated CPU |
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| 195 | vector number are specified to this directive. This directive |
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| 196 | installs the RTEMS interrupt wrapper in the processor's |
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| 197 | Interrupt Vector Table and the address of the user's ISR in the |
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| 198 | RTEMS' Vector Table. This directive returns the previous |
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| 199 | contents of the specified vector in the RTEMS' Vector Table. |
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| 200 | |
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| 201 | @ifinfo |
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| 202 | @node Directives Allowed from an ISR, Interrupt Manager Directives, Establishing an ISR, Interrupt Manager Operations |
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| 203 | @end ifinfo |
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| 204 | @subsection Directives Allowed from an ISR |
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| 205 | |
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| 206 | Using the interrupt manager insures that RTEMS knows |
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| 207 | when a directive is being called from an ISR. The ISR may then |
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| 208 | use system calls to synchronize itself with an application task. |
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| 209 | The synchronization may involve messages, events or signals |
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| 210 | being passed by the ISR to the desired task. Directives invoked |
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| 211 | by an ISR must operate only on objects which reside on the local |
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| 212 | node. The following is a list of RTEMS system calls that may be |
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| 213 | made from an ISR: |
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| 214 | |
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| 215 | @itemize @bullet |
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| 216 | @item Task Management |
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| 217 | |
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| 218 | @itemize - |
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| 219 | @item task_get_note, task_set_note, task_suspend, task_resume |
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| 220 | @end itemize |
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| 221 | |
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| 222 | @item Clock Management |
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| 223 | |
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| 224 | @itemize - |
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| 225 | @item clock_get, clock_tick |
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| 226 | @end itemize |
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| 227 | |
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| 228 | @item Message, Event, and Signal Management |
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| 229 | |
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| 230 | @itemize - |
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| 231 | @item message_queue_send, message_queue_urgent |
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| 232 | @item event_send |
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| 233 | @item signal_send |
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| 234 | @end itemize |
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| 235 | |
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| 236 | @item Semaphore Management |
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| 237 | |
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| 238 | @itemize - |
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| 239 | @item semaphore_release |
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| 240 | @end itemize |
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| 241 | |
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| 242 | @item Dual-Ported Memory Management |
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| 243 | |
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| 244 | @itemize - |
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| 245 | @item port_external_to_internal, port_internal_to_external |
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| 246 | @end itemize |
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| 247 | |
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| 248 | @item IO Management |
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| 249 | |
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| 250 | @itemize - |
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| 251 | @item io_initialize, io_open, io_close, io_read, io_write, io_control |
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| 252 | @end itemize |
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| 253 | |
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| 254 | @item Fatal Error Management |
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| 255 | |
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| 256 | @itemize - |
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| 257 | @item fatal_error_occurred |
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| 258 | @end itemize |
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| 259 | |
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| 260 | @item Multiprocessing |
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| 261 | |
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| 262 | @itemize - |
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| 263 | @item multiprocessing_announce |
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| 264 | @end itemize |
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| 265 | @end itemize |
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| 266 | |
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| 267 | @ifinfo |
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| 268 | @node Interrupt Manager Directives, INTERRUPT_CATCH - Establish an ISR, Directives Allowed from an ISR, Interrupt Manager |
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| 269 | @end ifinfo |
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| 270 | @section Directives |
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| 271 | @ifinfo |
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| 272 | @menu |
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| 273 | * INTERRUPT_CATCH - Establish an ISR:: |
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[a94c5a5d] | 274 | * INTERRUPT_DISABLE - Disable Interrupts:: |
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| 275 | * INTERRUPT_ENABLE - Enable Interrupts:: |
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| 276 | * INTERRUPT_FLASH - Flash Interrupts:: |
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| 277 | * INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress:: |
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[ae68ff0] | 278 | @end menu |
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| 279 | @end ifinfo |
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| 280 | |
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| 281 | This section details the interrupt manager's |
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| 282 | directives. A subsection is dedicated to each of this manager's |
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| 283 | directives and describes the calling sequence, related |
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| 284 | constants, usage, and status codes. |
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| 285 | |
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| 286 | @page |
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| 287 | @ifinfo |
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[a94c5a5d] | 288 | @node INTERRUPT_CATCH - Establish an ISR, INTERRUPT_DISABLE - Disable Interrupts, Interrupt Manager Directives, Interrupt Manager Directives |
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[ae68ff0] | 289 | @end ifinfo |
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| 290 | @subsection INTERRUPT_CATCH - Establish an ISR |
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| 291 | |
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| 292 | @subheading CALLING SEQUENCE: |
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| 293 | |
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[61389eac] | 294 | @ifset is-C |
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[ae68ff0] | 295 | @example |
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| 296 | rtems_status_code rtems_interrupt_catch( |
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| 297 | rtems_isr_entry new_isr_handler, |
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| 298 | rtems_vector_number vector, |
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| 299 | rtems_isr_entry *old_isr_handler |
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| 300 | ); |
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| 301 | @end example |
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[61389eac] | 302 | @end ifset |
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| 303 | |
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| 304 | @ifset is-Ada |
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| 305 | @example |
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| 306 | procedure Interrupt_Catch ( |
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| 307 | New_ISR_handler : in RTEMS.Address; |
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| 308 | Vector : in RTEMS.Vector_Number; |
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| 309 | Old_ISR_Handler : out RTEMS.Address; |
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| 310 | Result : out RTEMS.Status_Codes |
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| 311 | ); |
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| 312 | @end example |
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| 313 | @end ifset |
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[ae68ff0] | 314 | |
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| 315 | @subheading DIRECTIVE STATUS CODES: |
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| 316 | @code{SUCCESSFUL} - ISR established successfully@* |
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| 317 | @code{INVALID_NUMBER} - illegal vector number@* |
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[173c59c8] | 318 | @code{INVALID_ADDRESS} - illegal ISR entry point or invalid old_isr_handler |
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[ae68ff0] | 319 | |
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| 320 | @subheading DESCRIPTION: |
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| 321 | |
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| 322 | This directive establishes an interrupt service |
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| 323 | routine (ISR) for the specified interrupt vector number. The |
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[7e8a1fc] | 324 | @code{new_isr_handler} parameter specifies the entry point of the ISR. |
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[ae68ff0] | 325 | The entry point of the previous ISR for the specified vector is |
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[7e8a1fc] | 326 | returned in @code{old_isr_handler}. |
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[ae68ff0] | 327 | |
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| 328 | @subheading NOTES: |
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| 329 | |
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[a94c5a5d] | 330 | This directive will not cause the calling task to be preempted. |
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| 331 | |
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| 332 | @page |
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| 333 | @ifinfo |
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| 334 | @node INTERRUPT_DISABLE - Disable Interrupts, INTERRUPT_ENABLE - Enable Interrupts, INTERRUPT_CATCH - Establish an ISR, Interrupt Manager Directives |
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| 335 | @end ifinfo |
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| 336 | @subsection INTERRUPT_DISABLE - Disable Interrupts |
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| 337 | |
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| 338 | @subheading CALLING SEQUENCE: |
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| 339 | |
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| 340 | @ifset is-C |
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| 341 | @example |
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| 342 | void rtems_interrupt_disable( |
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| 343 | rtems_isr_level level |
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| 344 | ); |
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| 345 | @end example |
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| 346 | @end ifset |
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| 347 | |
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| 348 | @ifset is-Ada |
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| 349 | @example |
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| 350 | function Interrupt_Disable |
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| 351 | return RTEMS.ISR_Level; |
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| 352 | @end example |
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| 353 | @end ifset |
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| 354 | |
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| 355 | @subheading DIRECTIVE STATUS CODES: |
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| 356 | |
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| 357 | NONE |
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| 358 | |
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| 359 | @subheading DESCRIPTION: |
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| 360 | |
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| 361 | This directive disables all maskable interrupts and returns |
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| 362 | the previous @code{level}. A later invocation of the |
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| 363 | @code{rtems_interrupt_enable} directive should be used to |
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| 364 | restore the interrupt level. |
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| 365 | |
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| 366 | @subheading NOTES: |
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| 367 | |
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| 368 | This directive will not cause the calling task to be preempted. |
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| 369 | |
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| 370 | @ifset is-C |
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| 371 | @b{This directive is implemented as a macro which modifies the @code{level} |
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| 372 | parameter.} |
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| 373 | @end ifset |
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| 374 | |
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| 375 | @page |
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| 376 | @ifinfo |
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| 377 | @node INTERRUPT_ENABLE - Enable Interrupts, INTERRUPT_FLASH - Flash Interrupts, INTERRUPT_DISABLE - Disable Interrupts, Interrupt Manager Directives |
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| 378 | @end ifinfo |
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| 379 | @subsection INTERRUPT_ENABLE - Enable Interrupts |
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| 380 | |
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| 381 | @subheading CALLING SEQUENCE: |
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| 382 | |
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| 383 | @ifset is-C |
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| 384 | @example |
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| 385 | void rtems_interrupt_enable( |
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| 386 | rtems_isr_level level |
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| 387 | ); |
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| 388 | @end example |
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| 389 | @end ifset |
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| 390 | |
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| 391 | @ifset is-Ada |
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| 392 | @example |
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| 393 | procedure Interrupt_Enable ( |
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| 394 | Level : in RTEMS.ISR_Level |
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| 395 | ); |
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| 396 | @end example |
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| 397 | @end ifset |
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| 398 | |
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| 399 | @subheading DIRECTIVE STATUS CODES: |
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| 400 | |
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| 401 | NONE |
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| 402 | |
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| 403 | @subheading DESCRIPTION: |
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| 404 | |
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| 405 | This directive enables maskable interrupts to the @code{level} |
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| 406 | which was returned by a previous call to @code{rtems_interrupt_disable}. |
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| 407 | Immediately prior to invoking this directive, maskable interrupts should |
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| 408 | be disabled by a call to @code{rtems_interrupt_disable} and will be enabled |
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| 409 | when this directive returns to the caller. |
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| 410 | |
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| 411 | @subheading NOTES: |
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| 412 | |
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| 413 | This directive will not cause the calling task to be preempted. |
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| 414 | |
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| 415 | |
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| 416 | @page |
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| 417 | @ifinfo |
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| 418 | @node INTERRUPT_FLASH - Flash Interrupts, INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress, INTERRUPT_ENABLE - Enable Interrupts, Interrupt Manager Directives |
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| 419 | @end ifinfo |
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| 420 | @subsection INTERRUPT_FLASH - Flash Interrupts |
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| 421 | |
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| 422 | @subheading CALLING SEQUENCE: |
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| 423 | |
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| 424 | @ifset is-C |
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| 425 | @example |
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| 426 | void rtems_interrupt_flash( |
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| 427 | rtems_isr_level level |
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| 428 | ); |
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| 429 | @end example |
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| 430 | @end ifset |
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| 431 | |
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| 432 | @ifset is-Ada |
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| 433 | @example |
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| 434 | procedure Interrupt_Flash ( |
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| 435 | Level : in RTEMS.ISR_Level |
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| 436 | ); |
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| 437 | @end example |
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| 438 | @end ifset |
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| 439 | |
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| 440 | @subheading DIRECTIVE STATUS CODES: |
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| 441 | |
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| 442 | NONE |
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| 443 | |
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| 444 | @subheading DESCRIPTION: |
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| 445 | |
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| 446 | This directive temporarily enables maskable interrupts to the @code{level} |
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| 447 | which was returned by a previous call to @code{rtems_interrupt_disable}. |
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| 448 | Immediately prior to invoking this directive, maskable interrupts should |
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| 449 | be disabled by a call to @code{rtems_interrupt_disable} and will be redisabled |
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| 450 | when this directive returns to the caller. |
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| 451 | |
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| 452 | @subheading NOTES: |
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| 453 | |
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| 454 | This directive will not cause the calling task to be preempted. |
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| 455 | |
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| 456 | @page |
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| 457 | @ifinfo |
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| 458 | @node INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress, Clock Manager, INTERRUPT_FLASH - Flash Interrupts, Interrupt Manager Directives |
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| 459 | @end ifinfo |
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| 460 | @subsection INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress |
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| 461 | |
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| 462 | @subheading CALLING SEQUENCE: |
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| 463 | |
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| 464 | @ifset is-C |
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| 465 | @example |
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| 466 | rtems_boolean rtems_interrupt_is_in_progress( void ); |
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| 467 | @end example |
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| 468 | @end ifset |
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| 469 | |
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| 470 | @ifset is-Ada |
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| 471 | @example |
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| 472 | function Interrupt_Is_In_Progress |
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| 473 | return RTEMS.Boolean; |
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| 474 | @end example |
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| 475 | @end ifset |
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| 476 | |
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| 477 | @subheading DIRECTIVE STATUS CODES: |
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| 478 | |
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| 479 | NONE |
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| 480 | |
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| 481 | @subheading DESCRIPTION: |
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| 482 | |
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| 483 | This directive returns @code{TRUE} if the processor is currently |
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| 484 | servicing an interrupt and @code{FALSE} otherwise. A return value |
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| 485 | of @code{TRUE} indicates that the caller is an interrupt service |
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| 486 | routine, @b{NOT} a task. The directives available to an interrupt |
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| 487 | service routine are restricted. |
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| 488 | |
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| 489 | @subheading NOTES: |
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| 490 | |
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| 491 | This directive will not cause the calling task to be preempted. |
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[ae68ff0] | 492 | |
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