1 | @c |
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2 | @c COPYRIGHT (c) 1988-1999. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @include ../../common/timemac.texi |
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10 | @tex |
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11 | \global\advance \smallskipamount by -4pt |
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12 | @end tex |
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13 | |
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14 | @chapter BSP_FOR_TIMES Timing Data |
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15 | |
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16 | @section Introduction |
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17 | |
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18 | The timing data for the XXX version of RTEMS is |
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19 | provided along with the target dependent aspects concerning the |
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20 | gathering of the timing data. The hardware platform used to |
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21 | gather the times is described to give the reader a better |
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22 | understanding of each directive time provided. Also, provided |
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23 | is a description of the interrupt latency and the context switch |
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24 | times as they pertain to the XXX version of RTEMS. |
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25 | |
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26 | @section Hardware Platform |
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27 | |
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28 | All times reported except for the maximum period |
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29 | interrupts are disabled by RTEMS were measured using a Motorola |
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30 | BSP_FOR_TIMES CPU board. The BSP_FOR_TIMES is a 20Mhz board with one wait |
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31 | state dynamic memory and a XXX numeric coprocessor. The |
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32 | Zilog 8036 countdown timer on this board was used to measure |
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33 | elapsed time with a one-half microsecond resolution. All |
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34 | sources of hardware interrupts were disabled, although the |
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35 | interrupt level of the XXX allows all interrupts. |
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36 | |
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37 | The maximum period interrupts are disabled was |
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38 | measured by summing the number of CPU cycles required by each |
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39 | assembly language instruction executed while interrupts were |
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40 | disabled. The worst case times of the XXX microprocessor |
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41 | were used for each instruction. Zero wait state memory was |
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42 | assumed. The total CPU cycles executed with interrupts |
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43 | disabled, including the instructions to disable and enable |
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44 | interrupts, was divided by 20 to simulate a 20Mhz XXX. It |
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45 | should be noted that the worst case instruction times for the |
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46 | XXX assume that the internal cache is disabled and that no |
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47 | instructions overlap. |
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48 | |
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49 | @section Interrupt Latency |
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50 | |
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51 | The maximum period with interrupts disabled within |
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52 | RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD |
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53 | microseconds including the instructions |
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54 | which disable and re-enable interrupts. The time required for |
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55 | the XXX to vector an interrupt and for the RTEMS entry |
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56 | overhead before invoking the user's interrupt handler are a |
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57 | total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK |
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58 | microseconds. These combine to yield a worst case |
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59 | interrupt latency of less than |
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60 | RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK |
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61 | microseconds at 20Mhz. [NOTE: The maximum period with interrupts |
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62 | disabled was last determined for Release |
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63 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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64 | |
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65 | It should be noted again that the maximum period with |
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66 | interrupts disabled within RTEMS is hand-timed and based upon |
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67 | worst case (i.e. CPU cache disabled and no instruction overlap) |
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68 | times for a 20Mhz XXX. The interrupt vector and entry |
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69 | overhead time was generated on an BSP_FOR_TIMES benchmark platform |
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70 | using the Multiprocessing Communications registers to generate |
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71 | as the interrupt source. |
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72 | |
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73 | @section Context Switch |
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74 | |
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75 | The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS |
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76 | microseconds on the BSP_FOR_TIMES benchmark platform when no floating |
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77 | point context is saved or restored. Additional execution time |
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78 | is required when a TASK_SWITCH user extension is configured. |
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79 | The use of the TASK_SWITCH extension is application dependent. |
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80 | Thus, its execution time is not considered part of the raw |
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81 | context switch time. |
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82 | |
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83 | Since RTEMS was designed specifically for embedded |
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84 | missile applications which are floating point intensive, the |
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85 | executive is optimized to avoid unnecessarily saving and |
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86 | restoring the state of the numeric coprocessor. The state of |
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87 | the numeric coprocessor is only saved when an FLOATING_POINT |
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88 | task is dispatched and that task was not the last task to |
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89 | utilize the coprocessor. In a system with only one |
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90 | FLOATING_POINT task, the state of the numeric coprocessor will |
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91 | never be saved or restored. When the first FLOATING_POINT task |
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92 | is dispatched, RTEMS does not need to save the current state of |
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93 | the numeric coprocessor. |
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94 | |
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95 | The exact amount of time required to save and restore |
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96 | floating point context is dependent on whether an XXX or |
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97 | XXX is being used as well as the state of the numeric |
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98 | coprocessor. These numeric coprocessors define three operating |
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99 | states: initialized, idle, and busy. RTEMS places the |
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100 | coprocessor in the initialized state when a task is started or |
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101 | restarted. Once the task has utilized the coprocessor, it is in |
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102 | the idle state when floating point instructions are not |
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103 | executing and the busy state when floating point instructions |
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104 | are executing. The state of the coprocessor is task specific. |
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105 | |
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106 | The following table summarizes the context switch |
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107 | times for the BSP_FOR_TIMES benchmark platform: |
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108 | |
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