source: rtems/doc/supplements/sparc/preface.texi @ 6449498

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2001-01-17 Joel Sherrill <joel@…>

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1@c
2@c  COPYRIGHT (c) 1988-2002.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@ifinfo
10@node Preface, CPU Model Dependent Features, Top, Top
11@end ifinfo
12@unnumbered Preface
13
14The Real Time Executive for Multiprocessor Systems
15(RTEMS) is designed to be portable across multiple processor
16architectures.  However, the nature of real-time systems makes
17it essential that the application designer understand certain
18processor dependent implementation details.  These processor
19dependencies include calling convention, board support package
20issues, interrupt processing, exact RTEMS memory requirements,
21performance data, header files, and the assembly language
22interface to the executive.
23
24This document discusses the SPARC architecture
25dependencies in this port of RTEMS.  Currently, only
26implementations of SPARC Version 7 are supported by RTEMS.
27
28It is highly recommended that the SPARC RTEMS
29application developer obtain and become familiar with the
30documentation for the processor being used as well as the
31specification for the revision of the SPARC architecture which
32corresponds to that processor.
33
34@subheading SPARC Architecture Documents
35
36For information on the SPARC architecture, refer to
37the following documents available from SPARC International, Inc.
38(http://www.sparc.com):
39
40@itemize @bullet
41@item SPARC Standard Version 7.
42
43@item SPARC Standard Version 8.
44
45@item SPARC Standard Version 9.
46@end itemize
47
48@subheading ERC32 Specific Information
49
50The European Space Agency's ERC32 is a three chip
51computing core implementing a SPARC V7 processor and associated
52support circuitry for embedded space applications. The integer
53and floating-point units (90C601E & 90C602E) are based on the
54Cypress 7C601 and 7C602, with additional error-detection and
55recovery functions. The memory controller (MEC) implements
56system support functions such as address decoding, memory
57interface, DMA interface, UARTs, timers, interrupt control,
58write-protection, memory reconfiguration and error-detection.
59The core is designed to work at 25MHz, but using space qualified
60memories limits the system frequency to around 15 MHz, resulting
61in a performance of 10 MIPS and 2 MFLOPS.
62
63Information on the ERC32 and a number of development
64support tools, such as the SPARC Instruction Simulator (SIS),
65are freely available on the Internet.  The following documents
66and SIS are available via anonymous ftp or pointing your web
67browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
68
69@itemize @bullet
70@item ERC32 System Design Document
71
72@item MEC Device Specification
73@end itemize
74
75Additionally, the SPARC RISC User's Guide from Matra
76MHS documents the functionality of the integer and floating
77point units including the instruction set information.  To
78obtain this document as well as ERC32 components and VHDL models
79contact:
80
81@example
82Matra MHS SA
833 Avenue du Centre, BP 309,
8478054 St-Quentin-en-Yvelines,
85Cedex, France
86VOICE: +31-1-30607087
87FAX: +31-1-30640693
88@end example
89
90Amar Guennon (amar.guennon@@matramhs.fr) is familiar with the ERC32.
91
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