1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @node Preface, CPU Model Dependent Features, Top, Top |
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11 | @end ifinfo |
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12 | @unnumbered Preface |
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13 | |
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14 | The Real Time Executive for Multiprocessor Systems |
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15 | (RTEMS) is designed to be portable across multiple processor |
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16 | architectures. However, the nature of real-time systems makes |
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17 | it essential that the application designer understand certain |
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18 | processor dependent implementation details. These processor |
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19 | dependencies include calling convention, board support package |
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20 | issues, interrupt processing, exact RTEMS memory requirements, |
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21 | performance data, header files, and the assembly language |
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22 | interface to the executive. |
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23 | |
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24 | This document discusses the SPARC architecture |
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25 | dependencies in this port of RTEMS. Currently, only |
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26 | implementations of SPARC Version 7 are supported by RTEMS. |
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27 | |
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28 | It is highly recommended that the SPARC RTEMS |
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29 | application developer obtain and become familiar with the |
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30 | documentation for the processor being used as well as the |
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31 | specification for the revision of the SPARC architecture which |
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32 | corresponds to that processor. |
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33 | |
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34 | @subheading SPARC Architecture Documents |
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35 | |
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36 | For information on the SPARC architecture, refer to |
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37 | the following documents available from SPARC International, Inc. |
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38 | (http://www.sparc.com): |
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39 | |
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40 | @itemize @bullet |
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41 | @item SPARC Standard Version 7. |
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42 | |
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43 | @item SPARC Standard Version 8. |
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44 | |
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45 | @item SPARC Standard Version 9. |
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46 | @end itemize |
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47 | |
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48 | @subheading ERC32 Specific Information |
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49 | |
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50 | The European Space Agency's ERC32 is a three chip |
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51 | computing core implementing a SPARC V7 processor and associated |
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52 | support circuitry for embedded space applications. The integer |
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53 | and floating-point units (90C601E & 90C602E) are based on the |
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54 | Cypress 7C601 and 7C602, with additional error-detection and |
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55 | recovery functions. The memory controller (MEC) implements |
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56 | system support functions such as address decoding, memory |
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57 | interface, DMA interface, UARTs, timers, interrupt control, |
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58 | write-protection, memory reconfiguration and error-detection. |
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59 | The core is designed to work at 25MHz, but using space qualified |
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60 | memories limits the system frequency to around 15 MHz, resulting |
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61 | in a performance of 10 MIPS and 2 MFLOPS. |
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62 | |
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63 | Information on the ERC32 and a number of development |
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64 | support tools, such as the SPARC Instruction Simulator (SIS), |
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65 | are freely available on the Internet. The following documents |
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66 | and SIS are available via anonymous ftp or pointing your web |
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67 | browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. |
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68 | |
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69 | @itemize @bullet |
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70 | @item ERC32 System Design Document |
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71 | |
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72 | @item MEC Device Specification |
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73 | @end itemize |
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74 | |
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75 | Additionally, the SPARC RISC User's Guide from Matra |
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76 | MHS documents the functionality of the integer and floating |
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77 | point units including the instruction set information. To |
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78 | obtain this document as well as ERC32 components and VHDL models |
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79 | contact: |
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80 | |
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81 | @example |
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82 | Matra MHS SA |
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83 | 3 Avenue du Centre, BP 309, |
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84 | 78054 St-Quentin-en-Yvelines, |
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85 | Cedex, France |
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86 | VOICE: +31-1-30607087 |
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87 | FAX: +31-1-30640693 |
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88 | @end example |
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89 | |
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90 | Amar Guennon (amar.guennon@@matramhs.fr) is familiar with the ERC32. |
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91 | |
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