1 | @c |
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2 | @c COPYRIGHT (c) 1988-1998. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @chapter Memory Model |
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10 | |
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11 | @section Introduction |
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12 | |
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13 | A processor may support any combination of memory |
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14 | models ranging from pure physical addressing to complex demand |
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15 | paged virtual memory systems. RTEMS supports a flat memory |
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16 | model which ranges contiguously over the processor's allowable |
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17 | address space. RTEMS does not support segmentation or virtual |
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18 | memory of any kind. The appropriate memory model for RTEMS |
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19 | provided by the targeted processor and related characteristics |
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20 | of that model are described in this chapter. |
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21 | |
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22 | @section Flat Memory Model |
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23 | |
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24 | The SPARC architecture supports a flat 32-bit address |
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25 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
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26 | gigabytes). Each address is represented by a 32-bit value and |
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27 | is byte addressable. The address may be used to reference a |
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28 | single byte, half-word (2-bytes), word (4 bytes), or doubleword |
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29 | (8 bytes). Memory accesses within this address space are |
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30 | performed in big endian fashion by the SPARC. Memory accesses |
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31 | which are not properly aligned generate a "memory address not |
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32 | aligned" trap (type number 7). The following table lists the |
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33 | alignment requirements for a variety of data accesses: |
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34 | |
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35 | @ifset use-ascii |
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36 | @example |
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37 | @group |
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38 | +--------------+-----------------------+ |
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39 | | Data Type | Alignment Requirement | |
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40 | +--------------+-----------------------+ |
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41 | | byte | 1 | |
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42 | | half-word | 2 | |
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43 | | word | 4 | |
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44 | | doubleword | 8 | |
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45 | +--------------+-----------------------+ |
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46 | @end group |
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47 | @end example |
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48 | @end ifset |
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49 | |
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50 | @ifset use-tex |
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51 | @sp 1 |
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52 | @tex |
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53 | \centerline{\vbox{\offinterlineskip\halign{ |
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54 | \vrule\strut#& |
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55 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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56 | \vrule#& |
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57 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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58 | \vrule#\cr |
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59 | \noalign{\hrule} |
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60 | &\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule} |
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61 | &byte&&1&\cr\noalign{\hrule} |
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62 | &half-word&&2&\cr\noalign{\hrule} |
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63 | &word&&4&\cr\noalign{\hrule} |
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64 | &doubleword&&8&\cr\noalign{\hrule} |
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65 | }}\hfil} |
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66 | @end tex |
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67 | @end ifset |
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68 | |
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69 | @ifset use-html |
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70 | @html |
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71 | <CENTER> |
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72 | <TABLE COLS=2 WIDTH="60%" BORDER=2> |
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73 | <TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD> |
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74 | <TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR> |
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75 | <TR><TD ALIGN=center>byte</TD> |
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76 | <TD ALIGN=center>1</TD></TR> |
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77 | <TR><TD ALIGN=center>half-word</TD> |
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78 | <TD ALIGN=center>2</TD></TR> |
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79 | <TR><TD ALIGN=center>word</TD> |
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80 | <TD ALIGN=center>4</TD></TR> |
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81 | <TR><TD ALIGN=center>doubleword</TD> |
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82 | <TD ALIGN=center>8</TD></TR> |
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83 | </TABLE> |
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84 | </CENTER> |
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85 | @end html |
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86 | @end ifset |
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87 | |
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88 | Doubleword load and store operations must use a pair |
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89 | of registers as their source or destination. This pair of |
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90 | registers must be an adjacent pair of registers with the first |
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91 | of the pair being even numbered. For example, a valid |
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92 | destination for a doubleword load might be input registers 0 and |
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93 | 1 (i0 and i1). The pair i1 and i2 would be invalid. [NOTE: |
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94 | Some assemblers for the SPARC do not generate an error if an odd |
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95 | numbered register is specified as the beginning register of the |
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96 | pair. In this case, the assembler assumes that what the |
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97 | programmer meant was to use the even-odd pair which ends at the |
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98 | specified register. This may or may not have been a correct |
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99 | assumption.] |
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100 | |
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101 | RTEMS does not support any SPARC Memory Management |
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102 | Units, therefore, virtual memory or segmentation systems |
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103 | involving the SPARC are not supported. |
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104 | |
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