1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @chapter CPU Model Dependent Features |
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10 | |
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11 | @section Introduction |
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12 | |
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13 | Microprocessors are generally classified into |
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14 | families with a variety of CPU models or implementations within |
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15 | that family. Within a processor family, there is a high level |
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16 | of binary compatibility. This family may be based on either an |
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17 | architectural specification or on maintaining compatibility with |
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18 | a popular processor. Recent microprocessor families such as the |
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19 | SPARC or PA-RISC are based on an architectural specification |
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20 | which is independent or any particular CPU model or |
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21 | implementation. Older families such as the M68xxx and the iX86 |
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22 | evolved as the manufacturer strived to produce higher |
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23 | performance processor models which maintained binary |
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24 | compatibility with older models. |
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25 | |
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26 | RTEMS takes advantage of the similarity of the |
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27 | various models within a CPU family. Although the models do vary |
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28 | in significant ways, the high level of compatibility makes it |
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29 | possible to share the bulk of the CPU dependent executive code |
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30 | across the entire family. |
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31 | |
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32 | @section CPU Model Feature Flags |
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33 | |
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34 | Each processor family supported by RTEMS has a |
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35 | list of features which vary between CPU models |
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36 | within a family. For example, the most common model dependent |
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37 | feature regardless of CPU family is the presence or absence of a |
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38 | floating point unit or coprocessor. When defining the list of |
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39 | features present on a particular CPU model, one simply notes |
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40 | that floating point hardware is or is not present and defines a |
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41 | single constant appropriately. Conditional compilation is |
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42 | utilized to include the appropriate source code for this CPU |
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43 | model's feature set. It is important to note that this means |
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44 | that RTEMS is thus compiled using the appropriate feature set |
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45 | and compilation flags optimal for this CPU model used. The |
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46 | alternative would be to generate a binary which would execute on |
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47 | all family members using only the features which were always |
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48 | present. |
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49 | |
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50 | This section presents the set of features which vary |
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51 | across SPARC implementations and are of importance to RTEMS. |
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52 | The set of CPU model feature macros are defined in the file |
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53 | cpukit/score/cpu/sparc/sparc.h based upon the particular CPU |
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54 | model defined on the compilation command line. |
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55 | |
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56 | @subsection CPU Model Name |
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57 | |
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58 | The macro CPU_MODEL_NAME is a string which designates |
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59 | the name of this CPU model. For example, for the European Space |
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60 | Agency's ERC32 SPARC model, this macro is set to the string |
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61 | "erc32". |
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62 | |
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63 | @subsection Floating Point Unit |
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64 | |
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65 | The macro SPARC_HAS_FPU is set to 1 to indicate that |
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66 | this CPU model has a hardware floating point unit and 0 |
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67 | otherwise. |
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68 | |
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69 | @subsection Bitscan Instruction |
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70 | |
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71 | The macro SPARC_HAS_BITSCAN is set to 1 to indicate |
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72 | that this CPU model has the bitscan instruction. For example, |
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73 | this instruction is supported by the Fujitsu SPARClite family. |
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74 | |
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75 | @subsection Number of Register Windows |
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76 | |
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77 | The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to |
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78 | indicate the number of register window sets implemented by this |
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79 | CPU model. The SPARC architecture allows a for a maximum of |
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80 | thirty-two register window sets although most implementations |
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81 | only include eight. |
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82 | |
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83 | @subsection Low Power Mode |
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84 | |
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85 | The macro SPARC_HAS_LOW_POWER_MODE is set to one to |
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86 | indicate that this CPU model has a low power mode. If low power |
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87 | is enabled, then there must be CPU model specific implementation |
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88 | of the IDLE task in cpukit/score/cpu/sparc/cpu.c. The low |
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89 | power mode IDLE task should be of the form: |
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90 | |
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91 | @example |
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92 | while ( TRUE ) @{ |
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93 | enter low power mode |
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94 | @} |
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95 | @end example |
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96 | |
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97 | The code required to enter low power mode is CPU model specific. |
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98 | |
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99 | @section CPU Model Implementation Notes |
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100 | |
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101 | The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602 |
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102 | chipset. This CPU has a number of on-board peripherals and was developed by |
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103 | the European Space Agency to target space applications. RTEMS currently |
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104 | provides support for the following peripherals: |
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105 | |
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106 | @itemize @bullet |
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107 | @item UART Channels A and B |
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108 | @item General Purpose Timer |
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109 | @item Real Time Clock |
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110 | @item Watchdog Timer (so it can be disabled) |
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111 | @item Control Register (so powerdown mode can be enabled) |
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112 | @item Memory Control Register |
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113 | @item Interrupt Control |
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114 | @end itemize |
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115 | |
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116 | The General Purpose Timer and Real Time Clock Timer provided with the ERC32 |
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117 | share the Timer Control Register. Because the Timer Control Register is write |
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118 | only, we must mirror it in software and insure that writes to one timer do not |
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119 | alter the current settings and status of the other timer. Routines are |
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120 | provided in erc32.h which promote the view that the two timers are completely |
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121 | independent. By exclusively using these routines to access the Timer Control |
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122 | Register, the application can view the system as having a General Purpose |
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123 | Timer Control Register and a Real Time Clock Timer Control Register |
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124 | rather than the single shared value. |
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125 | |
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126 | The RTEMS Idle thread take advantage of the low power mode provided by the |
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127 | ERC32. Low power mode is entered during idle loops and is enabled at |
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128 | initialization time. |
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