1 | @c |
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2 | @c COPYRIGHT (c) 1988-1996. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | |
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7 | @ifinfo |
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8 | @node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top |
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9 | @end ifinfo |
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10 | @chapter Board Support Packages |
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11 | @ifinfo |
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12 | @menu |
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13 | * Board Support Packages Introduction:: |
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14 | * Board Support Packages System Reset:: |
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15 | * Board Support Packages Processor Initialization:: |
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16 | @end menu |
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17 | @end ifinfo |
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18 | |
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19 | @ifinfo |
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20 | @node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages |
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21 | @end ifinfo |
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22 | @section Introduction |
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23 | |
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24 | An RTEMS Board Support Package (BSP) must be designed |
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25 | to support a particular processor and target board combination. |
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26 | This chapter presents a discussion of SPARC specific BSP issues. |
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27 | For more information on developing a BSP, refer to the chapter |
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28 | titled Board Support Packages in the RTEMS |
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29 | Applications User's Guide. |
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30 | |
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31 | @ifinfo |
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32 | @node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages |
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33 | @end ifinfo |
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34 | @section System Reset |
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35 | |
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36 | An RTEMS based application is initiated or |
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37 | re-initiated when the SPARC processor is reset. When the SPARC |
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38 | is reset, the processor performs the following actions: |
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39 | |
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40 | @itemize @bullet |
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41 | @item the enable trap (ET) of the psr is set to 0 to disable |
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42 | traps, |
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43 | |
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44 | @item the supervisor bit (S) of the psr is set to 1 to enter |
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45 | supervisor mode, and |
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46 | |
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47 | @item the PC is set 0 and the nPC is set to 4. |
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48 | @end itemize |
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49 | |
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50 | The processor then begins to execute the code at |
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51 | location 0. It is important to note that all fields in the psr |
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52 | are not explicitly set by the above steps and all other |
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53 | registers retain their value from the previous execution mode. |
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54 | This is true even of the Trap Base Register (TBR) whose contents |
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55 | reflect the last trap which occurred before the reset. |
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56 | |
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57 | @ifinfo |
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58 | @node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages |
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59 | @end ifinfo |
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60 | @section Processor Initialization |
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61 | |
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62 | It is the responsibility of the application's |
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63 | initialization code to initialize the TBR and install trap |
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64 | handlers for at least the register window overflow and register |
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65 | window underflow conditions. Traps should be enabled before |
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66 | invoking any subroutines to allow for register window |
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67 | management. However, interrupts should be disabled by setting |
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68 | the Processor Interrupt Level (pil) field of the psr to 15. |
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69 | RTEMS installs it's own Trap Table as part of initialization |
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70 | which is initialized with the contents of the Trap Table in |
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71 | place when the rtems_initialize_executive directive was invoked. |
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72 | Upon completion of executive initialization, interrupts are |
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73 | enabled. |
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74 | |
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75 | If this SPARC implementation supports on-chip caching |
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76 | and this is to be utilized, then it should be enabled during the |
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77 | reset application initialization code. |
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78 | |
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79 | In addition to the requirements described in the |
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80 | Board Support Packages chapter of the @value{RTEMS-LANGUAGE} |
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81 | Applications User's Manual for the reset code |
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82 | which is executed before the call to |
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83 | rtems_initialize executive, the SPARC version has the following |
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84 | specific requirements: |
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85 | |
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86 | @itemize @bullet |
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87 | @item Must leave the S bit of the status register set so that |
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88 | the SPARC remains in the supervisor state. |
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89 | |
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90 | @item Must set stack pointer (sp) such that a minimum stack |
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91 | size of MINIMUM_STACK_SIZE bytes is provided for the |
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92 | rtems_initialize executive directive. |
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93 | |
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94 | @item Must disable all external interrupts (i.e. set the pil |
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95 | to 15). |
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96 | |
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97 | @item Must enable traps so window overflow and underflow |
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98 | conditions can be properly handled. |
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99 | |
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100 | @item Must initialize the SPARC's initial trap table with at |
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101 | least trap handlers for register window overflow and register |
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102 | window underflow. |
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103 | @end itemize |
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104 | |
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