1 | # |
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2 | # COPYRIGHT (c) 1988-2002. |
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3 | # On-Line Applications Research Corporation (OAR). |
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4 | # All rights reserved. |
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5 | # |
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6 | # $Id$ |
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7 | # |
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8 | |
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9 | |
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10 | PROJECT = sparc |
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11 | EDITION = 1 |
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12 | |
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13 | include $(top_srcdir)/project.am |
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14 | include $(top_srcdir)/supplements/supplement.am |
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15 | |
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16 | GENERATED_FILES = cpumodel.texi callconv.texi memmodel.texi intr.texi \ |
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17 | fatalerr.texi bsp.texi cputable.texi timing.texi wksheets.texi \ |
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18 | timeERC32.texi |
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19 | |
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20 | COMMON_FILES = $(top_srcdir)/common/setup.texi \ |
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21 | $(top_srcdir)/common/cpright.texi |
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22 | |
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23 | FILES = preface.texi |
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24 | |
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25 | info_TEXINFOS = sparc.texi |
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26 | sparc_TEXINFOS = $(FILES) $(COMMON_FILES) $(GENERATED_FILES) |
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27 | |
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28 | # |
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29 | # Chapters which get automatic processing |
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30 | # |
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31 | |
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32 | cpumodel.texi: cpumodel.t |
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33 | $(BMENU2) -p "Preface" \ |
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34 | -u "Top" \ |
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35 | -n "Calling Conventions" < $< > $@ |
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36 | |
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37 | callconv.texi: callconv.t |
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38 | $(BMENU2) -p "CPU Model Dependent Features CPU Model Implementation Notes" \ |
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39 | -u "Top" \ |
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40 | -n "Memory Model" < $< > $@ |
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41 | |
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42 | memmodel.texi: memmodel.t |
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43 | $(BMENU2) -p "Calling Conventions User-Provided Routines" \ |
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44 | -u "Top" \ |
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45 | -n "Interrupt Processing" < $< > $@ |
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46 | |
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47 | # Interrupt Chapter: |
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48 | # 1. Replace Times and Sizes |
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49 | # 2. Build Node Structure |
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50 | intr.texi: intr_NOTIMES.t ERC32_TIMES |
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51 | ${REPLACE2} -p $(srcdir)/ERC32_TIMES $(srcdir)/intr_NOTIMES.t | \ |
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52 | $(BMENU2) -p "Memory Model Flat Memory Model" \ |
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53 | -u "Top" \ |
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54 | -n "Default Fatal Error Processing" > $@ |
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55 | |
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56 | fatalerr.texi: fatalerr.t |
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57 | $(BMENU2) -p "Interrupt Processing Interrupt Stack" \ |
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58 | -u "Top" \ |
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59 | -n "Board Support Packages" < $< > $@ |
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60 | |
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61 | bsp.texi: bsp.t |
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62 | $(BMENU2) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \ |
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63 | -u "Top" \ |
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64 | -n "Processor Dependent Information Table" < $< > $@ |
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65 | |
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66 | cputable.texi: cputable.t |
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67 | $(BMENU2) -p "Board Support Packages Processor Initialization" \ |
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68 | -u "Top" \ |
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69 | -n "Memory Requirements" < $< > $@ |
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70 | |
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71 | # Worksheets Chapter: |
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72 | # 1. Obtain the Shared File |
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73 | # 2. Replace Times and Sizes |
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74 | # 3. Build Node Structure |
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75 | |
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76 | wksheets.texi: $(top_srcdir)/common/wksheets.t ERC32_TIMES |
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77 | ${REPLACE2} -p $(srcdir)/ERC32_TIMES $(top_srcdir)/common/wksheets.t | \ |
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78 | $(BMENU2) -p "Processor Dependent Information Table CPU Dependent Information Table" \ |
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79 | -u "Top" \ |
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80 | -n "Timing Specification" > $@ |
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81 | |
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82 | # Timing Specification Chapter: |
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83 | # 1. Copy the Shared File |
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84 | # 3. Build Node Structure |
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85 | timing.texi: $(top_srcdir)/common/timing.t |
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86 | $(BMENU2) -p "Memory Requirements RTEMS RAM Workspace Worksheet" \ |
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87 | -u "Top" \ |
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88 | -n "ERC32 Timing Data" < $< > $@ |
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89 | |
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90 | # Timing Data for ERC32 BSP Chapter: |
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91 | # 1. Copy the Shared File |
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92 | # 2. Replace Times and Sizes |
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93 | # 3. Build Node Structure |
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94 | |
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95 | timeERC32.texi: $(top_srcdir)/common/timetbl.t timeERC32.t |
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96 | cat $(srcdir)/timeERC32.t $(top_srcdir)/common/timetbl.t >timeERC32_.t |
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97 | @echo >>timeERC32_.t |
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98 | @echo "@tex" >>timeERC32_.t |
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99 | @echo "\\global\\advance \\smallskipamount by 4pt" >>timeERC32_.t |
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100 | @echo "@end tex" >>timeERC32_.t |
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101 | ${REPLACE2} -p $(srcdir)/ERC32_TIMES timeERC32_.t | \ |
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102 | $(BMENU2) -p "Timing Specification Terminology" \ |
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103 | -u "Top" \ |
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104 | -n "Command and Variable Index" > $@ |
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105 | CLEANFILES += timeERC32_.t |
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106 | |
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107 | EXTRA_DIST = ERC32_TIMES bsp.t callconv.t cpumodel.t cputable.t fatalerr.t \ |
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108 | intr_NOTIMES.t memmodel.t timeERC32.t |
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