source: rtems/doc/supplements/powerpc/timedata.t @ 6059e111

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Last change on this file since 6059e111 was 6059e111, checked in by Joel Sherrill <joel.sherrill@…>, on 08/04/97 at 20:04:43

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1@c
2@c  COPYRIGHT (c) 1988-1997.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@include ../common/timemac.texi
10@tex
11\global\advance \smallskipamount by -4pt
12@end tex
13
14@ifinfo
15@node PPC603e Timing Data, PPC603e Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
16@end ifinfo
17@chapter PPC603e Timing Data
18@ifinfo
19@menu
20* PPC603e Timing Data Introduction::
21* PPC603e Timing Data Hardware Platform::
22* PPC603e Timing Data Interrupt Latency::
23* PPC603e Timing Data Context Switch::
24* PPC603e Timing Data Directive Times::
25* PPC603e Timing Data Task Manager::
26* PPC603e Timing Data Interrupt Manager::
27* PPC603e Timing Data Clock Manager::
28* PPC603e Timing Data Timer Manager::
29* PPC603e Timing Data Semaphore Manager::
30* PPC603e Timing Data Message Manager::
31* PPC603e Timing Data Event Manager::
32* PPC603e Timing Data Signal Manager::
33* PPC603e Timing Data Partition Manager::
34* PPC603e Timing Data Region Manager::
35* PPC603e Timing Data Dual-Ported Memory Manager::
36* PPC603e Timing Data I/O Manager::
37* PPC603e Timing Data Rate Monotonic Manager::
38@end menu
39@end ifinfo
40
41@ifinfo
42@node PPC603e Timing Data Introduction, PPC603e Timing Data Hardware Platform, PPC603e Timing Data, PPC603e Timing Data
43@end ifinfo
44@section Introduction
45
46The timing data for RTEMS on the PPC603e implementation
47of the PowerPC architecture is provided along with the target
48dependent aspects concerning the gathering of the timing data.
49The hardware platform used to gather the times is described to
50give the reader a better understanding of each directive time
51provided.  Also, provided is a description of the interrupt
52latency and the context switch times as they pertain to the
53PowerPC version of RTEMS.
54
55@ifinfo
56@node PPC603e Timing Data Hardware Platform, PPC603e Timing Data Interrupt Latency, PPC603e Timing Data Introduction, PPC603e Timing Data
57@end ifinfo
58@section Hardware Platform
59
60All times reported in this chapter were measured using the PowerPC
61Instruction Simulator (PSIM). PSIM simulates a variety of PowerPC
626xx models with the PPC603e being used as the basis for the measurements
63reported in this chapter.
64
65The PowerPC decrementer register was was used to gather
66all timing information.  In real hardware implementations
67of the PowerPC architecture, this register would typically
68count something like CPU cycles or be a function of the clock
69speed.  However, wth PSIM each count of the decrementer register
70represents an instruction.  Thus all measurements in this
71chapter are reported as the actual number of instructions
72executed.  All sources of hardware interrupts were disabled,
73although traps were enabled and the interrupt level of the
74PowerPC allows all interrupts.
75
76@ifinfo
77@node PPC603e Timing Data Interrupt Latency, PPC603e Timing Data Context Switch, PPC603e Timing Data Hardware Platform, PPC603e Timing Data
78@end ifinfo
79@section Interrupt Latency
80
81The maximum period with traps disabled or the
82processor interrupt level set to it's highest value inside RTEMS
83is less than RTEMS_MAXIMUM_DISABLE_PERIOD
84microseconds including the instructions which
85disable and re-enable interrupts.  The time required for the
86PowerPC to vector an interrupt and for the RTEMS entry overhead
87before invoking the user's trap handler are a total of
88RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
89microseconds.  These combine to yield a worst case interrupt
90latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD +
91RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds at
92RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz.
93[NOTE:  The maximum period with interrupts disabled was last
94determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
95
96The maximum period with interrupts disabled within
97RTEMS is hand-timed with some assistance from PSIM.  The maximum
98period with interrupts disabled with RTEMS occurs .... XXX
99
100The interrupt vector and entry overhead time was
101generated on the PSIM benchmark platform using the PowerPC's
102decrementer register.  This register was programmed to generate
103an interrupt after one countdown.
104
105@ifinfo
106@node PPC603e Timing Data Context Switch, PPC603e Timing Data Directive Times, PPC603e Timing Data Interrupt Latency, PPC603e Timing Data
107@end ifinfo
108@section Context Switch
109
110The RTEMS processor context switch time is XXX
111microseconds on the PSIM benchmark platform when no floating
112point context is saved or restored.  Additional execution time
113is required when a TASK_SWITCH user extension is configured.
114The use of the TASK_SWITCH extension is application dependent.
115Thus, its execution time is not considered part of the raw
116context switch time.
117
118Since RTEMS was designed specifically for embedded
119missile applications which are floating point intensive, the
120executive is optimized to avoid unnecessarily saving and
121restoring the state of the numeric coprocessor.  The state of
122the numeric coprocessor is only saved when an FLOATING_POINT
123task is dispatched and that task was not the last task to
124utilize the coprocessor.  In a system with only one
125FLOATING_POINT task, the state of the numeric coprocessor will
126never be saved or restored.  When the first FLOATING_POINT task
127is dispatched, RTEMS does not need to save the current state of
128the numeric coprocessor.
129
130The following table summarizes the context switch
131times for the PSIM benchmark platform:
132
133@include timetbl.texi
134
135@tex
136\global\advance \smallskipamount by 4pt
137@end tex
138
139
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