1 | @c |
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2 | @c Timing information for PSIM |
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3 | @c |
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4 | @c COPYRIGHT (c) 1988-1999. |
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5 | @c On-Line Applications Research Corporation (OAR). |
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6 | @c All rights reserved. |
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7 | @c |
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8 | @c $Id$ |
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9 | @c |
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10 | |
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11 | @include common/timemac.texi |
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12 | @tex |
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13 | \global\advance \smallskipamount by -4pt |
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14 | @end tex |
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15 | |
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16 | @chapter RTEMS_BSP Timing Data |
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17 | |
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18 | @section Introduction |
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19 | |
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20 | The timing data for RTEMS on the RTEMS_BSP target |
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21 | is provided along with the target |
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22 | dependent aspects concerning the gathering of the timing data. |
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23 | The hardware platform used to gather the times is described to |
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24 | give the reader a better understanding of each directive time |
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25 | provided. Also, provided is a description of the interrupt |
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26 | latency and the context switch times as they pertain to the |
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27 | PowerPC version of RTEMS. |
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28 | |
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29 | @section Hardware Platform |
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30 | |
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31 | All times reported in this chapter were measured using the PowerPC |
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32 | Instruction Simulator (PSIM). PSIM simulates a variety of PowerPC |
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33 | 6xx models with the PPC603e being used as the basis for the measurements |
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34 | reported in this chapter. |
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35 | |
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36 | The PowerPC decrementer register was was used to gather |
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37 | all timing information. In real hardware implementations |
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38 | of the PowerPC architecture, this register would typically |
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39 | count something like CPU cycles or be a function of the clock |
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40 | speed. However, with PSIM each count of the decrementer register |
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41 | represents an instruction. Thus all measurements in this |
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42 | chapter are reported as the actual number of instructions |
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43 | executed. All sources of hardware interrupts were disabled, |
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44 | although traps were enabled and the interrupt level of the |
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45 | PowerPC allows all interrupts. |
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46 | |
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47 | @section Interrupt Latency |
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48 | |
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49 | The maximum period with traps disabled or the |
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50 | processor interrupt level set to it's highest value inside RTEMS |
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51 | is less than RTEMS_MAXIMUM_DISABLE_PERIOD |
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52 | microseconds including the instructions which |
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53 | disable and re-enable interrupts. The time required for the |
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54 | PowerPC to vector an interrupt and for the RTEMS entry overhead |
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55 | before invoking the user's trap handler are a total of |
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56 | RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK |
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57 | microseconds. These combine to yield a worst case interrupt |
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58 | latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD + |
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59 | RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds at |
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60 | RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz. |
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61 | [NOTE: The maximum period with interrupts disabled was last |
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62 | determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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63 | |
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64 | The maximum period with interrupts disabled within |
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65 | RTEMS is hand-timed with some assistance from RTEMS_BSP. The maximum |
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66 | period with interrupts disabled with RTEMS occurs was not measured |
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67 | on this target. |
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68 | |
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69 | The interrupt vector and entry overhead time was |
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70 | generated on the RTEMS_BSP benchmark platform using the PowerPC's |
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71 | decrementer register. This register was programmed to generate |
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72 | an interrupt after one countdown. |
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73 | |
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74 | @section Context Switch |
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75 | |
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76 | The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS |
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77 | instructions on the RTEMS_BSP benchmark platform when no floating |
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78 | point context is saved or restored. Additional execution time |
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79 | is required when a TASK_SWITCH user extension is configured. |
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80 | The use of the TASK_SWITCH extension is application dependent. |
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81 | Thus, its execution time is not considered part of the raw |
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82 | context switch time. |
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83 | |
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84 | Since RTEMS was designed specifically for embedded |
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85 | missile applications which are floating point intensive, the |
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86 | executive is optimized to avoid unnecessarily saving and |
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87 | restoring the state of the numeric coprocessor. The state of |
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88 | the numeric coprocessor is only saved when an FLOATING_POINT |
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89 | task is dispatched and that task was not the last task to |
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90 | utilize the coprocessor. In a system with only one |
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91 | FLOATING_POINT task, the state of the numeric coprocessor will |
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92 | never be saved or restored. When the first FLOATING_POINT task |
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93 | is dispatched, RTEMS does not need to save the current state of |
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94 | the numeric coprocessor. |
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95 | |
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96 | The following table summarizes the context switch |
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97 | times for the RTEMS_BSP benchmark platform: |
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