1 | @c |
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2 | @c COPYRIGHT (c) 1988-1998. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top |
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11 | @end ifinfo |
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12 | @chapter Memory Model |
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13 | @ifinfo |
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14 | @menu |
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15 | * Memory Model Introduction:: |
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16 | * Memory Model Flat Memory Model:: |
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17 | @end menu |
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18 | @end ifinfo |
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19 | |
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20 | @ifinfo |
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21 | @node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model |
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22 | @end ifinfo |
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23 | @section Introduction |
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24 | |
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25 | A processor may support any combination of memory |
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26 | models ranging from pure physical addressing to complex demand |
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27 | paged virtual memory systems. RTEMS supports a flat memory |
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28 | model which ranges contiguously over the processor's allowable |
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29 | address space. RTEMS does not support segmentation or virtual |
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30 | memory of any kind. The appropriate memory model for RTEMS |
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31 | provided by the targeted processor and related characteristics |
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32 | of that model are described in this chapter. |
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33 | |
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34 | @ifinfo |
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35 | @node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model |
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36 | @end ifinfo |
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37 | @section Flat Memory Model |
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38 | |
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39 | The PowerPC architecture supports a variety of memory models. |
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40 | RTEMS supports the PowerPC using a flat memory model with |
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41 | paging disabled. In this mode, the PowerPC automatically |
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42 | converts every address from a logical to a physical address |
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43 | each time it is used. The PowerPC uses information provided |
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44 | in the Block Address Translation (BAT) to convert these addresses. |
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45 | |
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46 | Implementations of the PowerPC architecture may be thirty-two or sixty-four bit. |
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47 | The PowerPC architecture supports a flat thirty-two or sixty-four bit address |
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48 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
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49 | gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF |
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50 | in sixty-four bit implementations. Each address is represented |
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51 | by either a thirty-two bit or sixty-four bit value and is byte addressable. |
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52 | The address may be used to reference a single byte, half-word |
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53 | (2-bytes), word (4 bytes), or in sixty-four bit implementations a |
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54 | doubleword (8 bytes). Memory accesses within the address space are |
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55 | performed in big or little endian fashion by the PowerPC based |
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56 | upon the current setting of the Little-endian mode enable bit (LE) |
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57 | in the Machine State Register (MSR). While the processor is in |
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58 | big endian mode, memory accesses which are not properly aligned |
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59 | generate an "alignment exception" (vector offset 0x00600). In |
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60 | little endian mode, the PowerPC architecture does not require |
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61 | the processor to generate alignment exceptions. |
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62 | |
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63 | The following table lists the alignment requirements for a variety |
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64 | of data accesses: |
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65 | |
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66 | @ifset use-ascii |
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67 | @example |
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68 | @group |
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69 | +--------------+-----------------------+ |
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70 | | Data Type | Alignment Requirement | |
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71 | +--------------+-----------------------+ |
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72 | | byte | 1 | |
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73 | | half-word | 2 | |
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74 | | word | 4 | |
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75 | | doubleword | 8 | |
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76 | +--------------+-----------------------+ |
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77 | @end group |
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78 | @end example |
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79 | @end ifset |
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80 | |
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81 | @ifset use-tex |
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82 | @sp 1 |
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83 | @tex |
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84 | \centerline{\vbox{\offinterlineskip\halign{ |
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85 | \vrule\strut#& |
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86 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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87 | \vrule#& |
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88 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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89 | \vrule#\cr |
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90 | \noalign{\hrule} |
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91 | &\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule} |
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92 | &byte&&1&\cr\noalign{\hrule} |
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93 | &half-word&&2&\cr\noalign{\hrule} |
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94 | &word&&4&\cr\noalign{\hrule} |
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95 | &doubleword&&8&\cr\noalign{\hrule} |
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96 | }}\hfil} |
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97 | @end tex |
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98 | @end ifset |
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99 | |
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100 | @ifset use-html |
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101 | @html |
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102 | <CENTER> |
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103 | <TABLE COLS=2 WIDTH="60%" BORDER=2> |
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104 | <TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD> |
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105 | <TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR> |
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106 | <TR><TD ALIGN=center>byte</TD> |
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107 | <TD ALIGN=center>1</TD></TR> |
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108 | <TR><TD ALIGN=center>half-word</TD> |
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109 | <TD ALIGN=center>2</TD></TR> |
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110 | <TR><TD ALIGN=center>word</TD> |
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111 | <TD ALIGN=center>4</TD></TR> |
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112 | <TR><TD ALIGN=center>doubleword</TD> |
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113 | <TD ALIGN=center>8</TD></TR> |
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114 | </TABLE> |
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115 | </CENTER> |
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116 | @end html |
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117 | @end ifset |
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118 | |
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119 | Doubleword load and store operations are only available in |
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120 | PowerPC CPU models which are sixty-four bit implementations. |
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121 | |
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122 | RTEMS does not directly support any PowerPC Memory Management |
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123 | Units, therefore, virtual memory or segmentation systems |
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124 | involving the PowerPC are not supported. |
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125 | |
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