source: rtems/doc/supplements/powerpc/memmodel.t @ abb3c75

4.104.114.84.95
Last change on this file since abb3c75 was abb3c75, checked in by Joel Sherrill <joel.sherrill@…>, on 08/13/98 at 21:17:35

Added DMV177 times files and made this all regenerate with two timing
chapters.

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1@c
2@c  COPYRIGHT (c) 1988-1998.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@ifinfo
10@node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top
11@end ifinfo
12@chapter Memory Model
13@ifinfo
14@menu
15* Memory Model Introduction::
16* Memory Model Flat Memory Model::
17@end menu
18@end ifinfo
19
20@ifinfo
21@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model
22@end ifinfo
23@section Introduction
24
25A processor may support any combination of memory
26models ranging from pure physical addressing to complex demand
27paged virtual memory systems.  RTEMS supports a flat memory
28model which ranges contiguously over the processor's allowable
29address space.  RTEMS does not support segmentation or virtual
30memory of any kind.  The appropriate memory model for RTEMS
31provided by the targeted processor and related characteristics
32of that model are described in this chapter.
33
34@ifinfo
35@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model
36@end ifinfo
37@section Flat Memory Model
38
39The PowerPC architecture supports a variety of memory models.
40RTEMS supports the PowerPC using a flat memory model with
41paging disabled.  In this mode, the PowerPC automatically
42converts every address from a logical to a physical address
43each time it is used.  The PowerPC uses information provided
44in the Block Address Translation (BAT) to convert these addresses.
45
46Implementations of the PowerPC architecture may be thirty-two or sixty-four bit.
47The PowerPC architecture supports a flat thirty-two or sixty-four bit address
48space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
49gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF
50in sixty-four bit implementations.  Each address is represented
51by either a thirty-two bit or sixty-four bit value and is byte addressable. 
52The address may be used to reference a single byte, half-word
53(2-bytes), word (4 bytes), or in sixty-four bit implementations a
54doubleword (8 bytes).  Memory accesses within the address space are
55performed in big or little endian fashion by the PowerPC based
56upon the current setting of the Little-endian mode enable bit (LE)
57in the Machine State Register (MSR).  While the processor is in
58big endian mode, memory accesses which are not properly aligned
59generate an "alignment exception" (vector offset 0x00600).  In
60little endian mode, the PowerPC architecture does not require
61the processor to generate alignment exceptions.
62
63The following table lists the alignment requirements for a variety
64of data accesses:
65
66@ifset use-ascii
67@example
68@group
69          +--------------+-----------------------+
70          |   Data Type  | Alignment Requirement |
71          +--------------+-----------------------+
72          |     byte     |          1            |
73          |   half-word  |          2            |
74          |     word     |          4            |
75          |  doubleword  |          8            |
76          +--------------+-----------------------+
77@end group
78@end example
79@end ifset
80
81@ifset use-tex
82@sp 1
83@tex
84\centerline{\vbox{\offinterlineskip\halign{
85\vrule\strut#&
86\hbox to 1.75in{\enskip\hfil#\hfil}&
87\vrule#&
88\hbox to 1.75in{\enskip\hfil#\hfil}&
89\vrule#\cr
90\noalign{\hrule}
91&\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule}
92&byte&&1&\cr\noalign{\hrule}
93&half-word&&2&\cr\noalign{\hrule}
94&word&&4&\cr\noalign{\hrule}
95&doubleword&&8&\cr\noalign{\hrule}
96}}\hfil}
97@end tex
98@end ifset
99 
100@ifset use-html
101@html
102<CENTER>
103  <TABLE COLS=2 WIDTH="60%" BORDER=2>
104<TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD>
105    <TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR>
106<TR><TD ALIGN=center>byte</TD>
107    <TD ALIGN=center>1</TD></TR>
108<TR><TD ALIGN=center>half-word</TD>
109    <TD ALIGN=center>2</TD></TR>
110<TR><TD ALIGN=center>word</TD>
111    <TD ALIGN=center>4</TD></TR>
112<TR><TD ALIGN=center>doubleword</TD>
113    <TD ALIGN=center>8</TD></TR>
114  </TABLE>
115</CENTER>
116@end html
117@end ifset
118
119Doubleword load and store operations are only available in
120PowerPC CPU models which are sixty-four bit implementations.
121
122RTEMS does not directly support any PowerPC Memory Management
123Units, therefore, virtual memory or segmentation systems
124involving the PowerPC  are not supported.
125
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