1 | @c |
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2 | @c COPYRIGHT (c) 1988-1997. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top |
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11 | @end ifinfo |
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12 | @chapter Interrupt Processing |
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13 | @ifinfo |
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14 | @menu |
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15 | * Interrupt Processing Introduction:: |
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16 | * Interrupt Processing Synchronous Versus Asynchronous Exceptions:: |
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17 | * Interrupt Processing Vectoring of Interrupt Handler:: |
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18 | * Interrupt Processing Interrupt Levels:: |
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19 | * Interrupt Processing Disabling of Interrupts by RTEMS:: |
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20 | * Interrupt Processing Interrupt Stack:: |
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21 | @end menu |
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22 | @end ifinfo |
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23 | |
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24 | @ifinfo |
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25 | @node Interrupt Processing Introduction, Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing, Interrupt Processing |
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26 | @end ifinfo |
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27 | @section Introduction |
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28 | |
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29 | Different types of processors respond to the |
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30 | occurrence of an interrupt in its own unique fashion. In |
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31 | addition, each processor type provides a control mechanism to |
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32 | allow for the proper handling of an interrupt. The processor |
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33 | dependent response to the interrupt modifies the current |
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34 | execution state and results in a change in the execution stream. |
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35 | Most processors require that an interrupt handler utilize some |
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36 | special control mechanisms to return to the normal processing |
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37 | stream. Although RTEMS hides many of the processor dependent |
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38 | details of interrupt processing, it is important to understand |
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39 | how the RTEMS interrupt manager is mapped onto the processor's |
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40 | unique architecture. Discussed in this chapter are the PPC's |
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41 | interrupt response and control mechanisms as they pertain to |
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42 | RTEMS. |
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43 | |
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44 | RTEMS and associated documentation uses the terms |
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45 | interrupt and vector. In the PPC architecture, these terms |
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46 | correspond to exception and exception handler, respectively. The terms will |
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47 | be used interchangeably in this manual. |
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48 | |
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49 | @ifinfo |
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50 | @node Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Introduction, Interrupt Processing |
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51 | @end ifinfo |
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52 | @section Synchronous Versus Asynchronous Exceptions |
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53 | |
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54 | In the PPC architecture exceptions can be either precise or |
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55 | imprecise and either synchronous or asynchronous. Asynchronous |
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56 | exceptions occur when an external event interrupts the processor. |
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57 | Synchronous exceptions are caused by the actions of an |
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58 | instruction. During an exception SRR0 is used to calculate where |
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59 | instruction processing should resume. All instructions prior to |
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60 | the resume instruction will have completed execution. SRR1 is used to |
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61 | store the machine status. |
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62 | |
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63 | There are two asynchronous nonmaskable, highest-priority exceptions |
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64 | system reset and machine check. There are two asynchrononous maskable |
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65 | low-priority exceptions external interrupt and decrementer. Nonmaskable |
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66 | execptions are never delayed, therefore if two nonmaskable, asynchronous |
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67 | exceptions occur in immediate succession, the state information saved by |
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68 | the first exception may be overwritten when the subsequent exception occurs. |
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69 | |
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70 | The PowerPC arcitecure defines one imprecise exception, the imprecise |
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71 | floating point enabled exception. All other synchronous exceptions are |
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72 | precise. The synchronization occuring during asynchronous precise |
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73 | exceptions conforms to the requirements for context synchronization. |
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74 | |
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75 | @ifinfo |
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76 | @node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Levels, Interrupt Processing Synchronous Versus Asynchronous Exceptions, Interrupt Processing |
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77 | @end ifinfo |
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78 | @section Vectoring of Interrupt Handler |
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79 | |
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80 | Upon determining that an exception can be taken the PPC automatically |
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81 | performs the following actions: |
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82 | |
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83 | @itemize @bullet |
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84 | @item an instruction address is loaded into SRR0 |
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85 | |
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86 | @item bits 33-36 and 42-47 of SRR1 are loaded with information |
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87 | specific to the exception. |
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88 | |
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89 | @item bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding |
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90 | bits from the MSR. |
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91 | |
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92 | @item the MSR is set based upon the exception type. |
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93 | |
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94 | @item instruction fetch and execution resumes, using the new MSR value, at a location specific to the execption type. |
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95 | |
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96 | @end itemize |
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97 | |
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98 | |
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99 | If the interrupt handler was installed as an RTEMS |
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100 | interrupt handler, then upon receipt of the interrupt, the |
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101 | processor passes control to the RTEMS interrupt handler which |
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102 | performs the following actions: |
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103 | |
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104 | @itemize @bullet |
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105 | @item saves the state of the interrupted task on it's stack, |
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106 | |
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107 | @item insures that a register window is available for |
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108 | subsequent exceptions, |
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109 | |
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110 | @item if this is the outermost (i.e. non-nested) interrupt, |
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111 | then the RTEMS interrupt handler switches from the current stack |
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112 | to the interrupt stack, |
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113 | |
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114 | @item enables exceptions, |
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115 | |
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116 | @item invokes the vectors to a user interrupt service routine (ISR). |
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117 | @end itemize |
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118 | |
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119 | Asynchronous interrupts are ignored while exceptions are |
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120 | disabled. Synchronous interrupts which occur while are |
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121 | disabled result in the CPU being forced into an error mode. |
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122 | |
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123 | A nested interrupt is processed similarly with the |
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124 | exception that the current stack need not be switched to the |
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125 | interrupt stack. |
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126 | |
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127 | @ifinfo |
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128 | @node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing |
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129 | @end ifinfo |
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130 | @section Interrupt Levels |
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131 | |
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132 | TBD levels (0-TBD) of interrupt priorities are |
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133 | supported by the PowerPC architecture with level TBD (TBD) |
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134 | being the highest priority. Level zero (0) indicates that |
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135 | interrupts are fully enabled. Interrupt requests for interrupts |
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136 | with priorities less than or equal to the current interrupt mask |
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137 | level are ignored. |
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138 | |
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139 | TBD |
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140 | All other RTEMS interrupt levels are undefined and their behavior is |
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141 | unpredictable. |
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142 | |
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143 | @ifinfo |
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144 | @node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing |
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145 | @end ifinfo |
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146 | @section Disabling of Interrupts by RTEMS |
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147 | |
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148 | During the execution of directive calls, critical |
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149 | sections of code may be executed. When these sections are |
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150 | encountered, RTEMS disables interrupts to level TBD (TBD) |
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151 | before the execution of this section and restores them to the |
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152 | previous level upon completion of the section. RTEMS has been |
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153 | optimized to insure that interrupts are disabled for less than |
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154 | RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a |
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155 | RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz PowerPC 603e with zero |
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156 | wait states. These numbers will vary based the number of wait |
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157 | states and processor speed present on the target board. |
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158 | [NOTE: The maximum period with interrupts disabled is hand calculated. This |
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159 | calculation was last performed for Release |
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160 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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161 | |
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162 | [NOTE: It is thought that the length of time at which |
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163 | the processor interrupt level is elevated to fifteen by RTEMS is |
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164 | not anywhere near as long as the length of time ALL exceptions are |
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165 | disabled as part of the "flush all register windows" operation.] |
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166 | |
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167 | Non-maskable interrupts (NMI) cannot be disabled, and |
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168 | ISRs which execute at this level MUST NEVER issue RTEMS system |
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169 | calls. If a directive is invoked, unpredictable results may |
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170 | occur due to the inability of RTEMS to protect its critical |
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171 | sections. However, ISRs that make no system calls may safely |
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172 | execute as non-maskable interrupts. |
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173 | |
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174 | @ifinfo |
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175 | @node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing |
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176 | @end ifinfo |
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177 | @section Interrupt Stack |
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178 | |
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179 | The PowerPC architecture does not provide for a |
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180 | dedicated interrupt stack. Thus by default, exception handlers would |
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181 | execute on the stack of the RTEMS task which they interrupted. |
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182 | This artificially inflates the stack requirements for each task |
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183 | since EVERY task stack would have to include enough space to |
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184 | account for the worst case interrupt stack requirements in |
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185 | addition to it's own worst case usage. RTEMS addresses this |
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186 | problem on the PowerPC by providing a dedicated interrupt stack |
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187 | managed by software. |
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188 | |
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189 | During system initialization, RTEMS allocates the |
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190 | interrupt stack from the Workspace Area. The amount of memory |
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191 | allocated for the interrupt stack is determined by the |
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192 | interrupt_stack_size field in the CPU Configuration Table. As |
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193 | part of processing a non-nested interrupt, RTEMS will switch to |
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194 | the interrupt stack before invoking the installed handler. |
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195 | |
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196 | |
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197 | |
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