1 | @c |
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2 | @c COPYRIGHT (c) 1988-1998. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @chapter CPU Model Dependent Features |
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10 | |
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11 | @section Introduction |
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12 | |
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13 | Microprocessors are generally classified into |
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14 | families with a variety of CPU models or implementations within |
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15 | that family. Within a processor family, there is a high level |
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16 | of binary compatibility. This family may be based on either an |
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17 | architectural specification or on maintaining compatibility with |
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18 | a popular processor. Recent microprocessor families such as the |
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19 | PowerPC, SPARC, and PA-RISC are based on an architectural specification |
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20 | which is independent or any particular CPU model or |
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21 | implementation. Older families such as the M68xxx and the iX86 |
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22 | evolved as the manufacturer strived to produce higher |
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23 | performance processor models which maintained binary |
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24 | compatibility with older models. |
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25 | |
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26 | RTEMS takes advantage of the similarity of the |
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27 | various models within a CPU family. Although the models do vary |
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28 | in significant ways, the high level of compatibility makes it |
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29 | possible to share the bulk of the CPU dependent executive code |
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30 | across the entire family. |
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31 | |
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32 | @section CPU Model Feature Flags |
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33 | |
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34 | Each processor family supported by RTEMS has a |
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35 | list of features which vary between CPU models |
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36 | within a family. For example, the most common model dependent |
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37 | feature regardless of CPU family is the presence or absence of a |
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38 | floating point unit or coprocessor. When defining the list of |
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39 | features present on a particular CPU model, one simply notes |
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40 | that floating point hardware is or is not present and defines a |
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41 | single constant appropriately. Conditional compilation is |
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42 | utilized to include the appropriate source code for this CPU |
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43 | model's feature set. It is important to note that this means |
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44 | that RTEMS is thus compiled using the appropriate feature set |
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45 | and compilation flags optimal for this CPU model used. The |
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46 | alternative would be to generate a binary which would execute on |
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47 | all family members using only the features which were always |
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48 | present. |
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49 | |
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50 | This section presents the set of features which vary |
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51 | across PowerPC implementations and are of importance to RTEMS. |
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52 | The set of CPU model feature macros are defined in the file |
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53 | c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU |
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54 | model defined on the compilation command line. |
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55 | |
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56 | @subsection CPU Model Name |
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57 | |
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58 | The macro CPU_MODEL_NAME is a string which designates |
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59 | the name of this CPU model. For example, for the PowerPC 603e |
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60 | model, this macro is set to the string "PowerPC 603e". |
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61 | |
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62 | @subsection Floating Point Unit |
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63 | |
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64 | The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model |
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65 | has a hardware floating point unit and 0 otherwise. |
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66 | |
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67 | @subsection Alignment |
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68 | |
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69 | The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment |
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70 | requirement for data types on a byte boundary. This value is used |
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71 | to derive the alignment restrictions for memory allocated from |
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72 | regions and partitions. |
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73 | |
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74 | @subsection Cache Alignment |
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75 | |
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76 | The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is |
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77 | used to align the entry point of critical routines so that as much code |
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78 | as possible can be retrieved with the initial read into cache. This |
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79 | is done for the interrupt handler as well as the context switch routines. |
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80 | |
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81 | In addition, the "shortcut" data structure used by the PowerPC implementation |
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82 | to ease access to data elements frequently accessed by RTEMS routines |
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83 | implemented in assembly language is aligned using this value. |
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84 | |
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85 | @subsection Maximum Interrupts |
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86 | |
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87 | The macro PPC_INTERRUPT_MAX is set to the number of exception sources |
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88 | supported by this PowerPC model. |
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89 | |
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90 | @subsection Has Double Precision Floating Point |
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91 | |
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92 | The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model |
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93 | has support for double precision floating point numbers. This is |
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94 | important because the floating point registers need only be four bytes |
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95 | wide (not eight) if double precision is not supported. |
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96 | |
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97 | @subsection Critical Interrupts |
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98 | |
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99 | The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model |
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100 | has the Critical Interrupt capability as defined by the IBM 403 models. |
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101 | |
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102 | @subsection Use Multiword Load/Store Instructions |
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103 | |
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104 | The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and |
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105 | store instructions should be used to perform context switch operations. |
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106 | The relative efficiency of multiword load and store instructions versus |
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107 | an equivalent set of single word load and store instructions varies based |
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108 | upon the PowerPC model. |
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109 | |
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110 | @subsection Instruction Cache Size |
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111 | |
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112 | The macro PPC_I_CACHE is set to the size in bytes of the instruction cache. |
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113 | |
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114 | @subsection Data Cache Size |
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115 | |
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116 | The macro PPC_D_CACHE is set to the size in bytes of the data cache. |
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117 | |
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118 | @subsection Debug Model |
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119 | |
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120 | The macro PPC_DEBUG_MODEL is set to indicate the debug support features |
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121 | present in this CPU model. The following debug support feature sets |
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122 | are currently supported: |
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123 | |
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124 | @table @b |
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125 | |
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126 | @item @code{PPC_DEBUG_MODEL_STANDARD} |
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127 | indicates that the single-step trace enable (SE) and branch trace |
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128 | enable (BE) bits in the MSR are supported by this CPU model. |
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129 | |
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130 | @item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY} |
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131 | indicates that only the single-step trace enable (SE) bit in the MSR |
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132 | is supported by this CPU model. |
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133 | |
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134 | @item @code{PPC_DEBUG_MODEL_IBM4xx} |
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135 | indicates that the debug exception enable (DE) bit in the MSR is supported |
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136 | by this CPU model. At this time, this particular debug feature set |
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137 | has only been seen in the IBM 4xx series. |
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138 | |
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139 | @end table |
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140 | |
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141 | @subsection Low Power Model |
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142 | |
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143 | The macro PPC_LOW_POWER_MODE is set to indicate the low power model |
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144 | supported by this CPU model. The following low power modes are currently |
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145 | supported. |
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146 | |
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147 | @table @b |
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148 | |
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149 | @item @code{PPC_LOW_POWER_MODE_NONE} |
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150 | indicates that this CPU model has no low power mode support. |
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151 | |
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152 | @item @code{PPC_LOW_POWER_MODE_STANDARD} |
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153 | indicates that this CPU model follows the low power model defined for |
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154 | the PPC603e. |
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155 | |
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156 | @end table |
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