source: rtems/doc/supplements/powerpc/cpumodel.t @ 563f7e0

4.104.114.84.95
Last change on this file since 563f7e0 was 563f7e0, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 1, 1997 at 6:39:44 PM

New files -- PowerPC supplement is based on the SPARC supplement.
This version has had some initial work done to convert it to
be PowerPC specific.

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File size: 7.9 KB
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1@c
2@c  COPYRIGHT (c) 1988-1996.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@ifinfo
10@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top
11@end ifinfo
12@chapter CPU Model Dependent Features
13@ifinfo
14@menu
15* CPU Model Dependent Features Introduction::
16* CPU Model Dependent Features CPU Model Feature Flags::
17* CPU Model Dependent Features CPU Model Implementation Notes::
18@end menu
19@end ifinfo
20
21@ifinfo
22@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features, CPU Model Dependent Features
23@end ifinfo
24@section Introduction
25
26Microprocessors are generally classified into
27families with a variety of CPU models or implementations within
28that family.  Within a processor family, there is a high level
29of binary compatibility.  This family may be based on either an
30architectural specification or on maintaining compatibility with
31a popular processor.  Recent microprocessor families such as the
32PowerPC, SPARC, and PA-RISC are based on an architectural specification
33which is independent or any particular CPU model or
34implementation.  Older families such as the M68xxx and the iX86
35evolved as the manufacturer strived to produce higher
36performance processor models which maintained binary
37compatibility with older models.
38
39RTEMS takes advantage of the similarity of the
40various models within a CPU family.  Although the models do vary
41in significant ways, the high level of compatibility makes it
42possible to share the bulk of the CPU dependent executive code
43across the entire family.
44
45@ifinfo
46@node CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Introduction, CPU Model Dependent Features
47@end ifinfo
48@section CPU Model Feature Flags
49@ifinfo
50@menu
51* CPU Model Dependent Features CPU Model Name::
52* CPU Model Dependent Features Floating Point Unit::
53* CPU Model Dependent Features Alignment::
54* CPU Model Dependent Features Cache Alignment::
55* CPU Model Dependent Features Maximum Interrupts::
56* CPU Model Dependent Features Has Double Precision Floating Point::
57* CPU Model Dependent Features Critical Interrupts::
58* CPU Model Dependent Features MSR Values::
59* CPU Model Dependent Features FPU Status Control Register Values::
60* CPU Model Dependent Features Use Multiword Load/Store Instructions::
61* CPU Model Dependent Features Instruction Cache Size::
62* CPU Model Dependent Features Data Cache Size::
63@end menu
64@end ifinfo
65
66Each processor family supported by RTEMS has a
67list of features which vary between CPU models
68within a family.  For example, the most common model dependent
69feature regardless of CPU family is the presence or absence of a
70floating point unit or coprocessor.  When defining the list of
71features present on a particular CPU model, one simply notes
72that floating point hardware is or is not present and defines a
73single constant appropriately.  Conditional compilation is
74utilized to include the appropriate source code for this CPU
75model's feature set.  It is important to note that this means
76that RTEMS is thus compiled using the appropriate feature set
77and compilation flags optimal for this CPU model used.  The
78alternative would be to generate a binary which would execute on
79all family members using only the features which were always
80present.
81
82This section presents the set of features which vary
83across PowerPC implementations and are of importance to RTEMS.
84The set of CPU model feature macros are defined in the file
85c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU
86model defined on the compilation command line.
87
88@ifinfo
89@node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Feature Flags
90@end ifinfo
91@subsection CPU Model Name
92
93The macro CPU_MODEL_NAME is a string which designates
94the name of this CPU model.  For example, for the PowerPC 603e
95model, this macro is set to the string "PowerPC 603e".
96
97@ifinfo
98@node CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Alignment, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features CPU Model Feature Flags
99@end ifinfo
100@subsection Floating Point Unit
101
102The macro PPC_HAS_FPU is set to 1 to indicate that
103this CPU model has a hardware floating point unit and 0
104otherwise.
105
106@ifinfo
107@node CPU Model Dependent Features Alignment, CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags
108@end ifinfo
109@subsection Alignment
110
111The macro PPC_ALIGNMENT is set to
112
113@ifinfo
114@node CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features Alignment, CPU Model Dependent Features CPU Model Feature Flags
115@end ifinfo
116@subsection Cache Alignment
117
118The macro PPC_CACHE_ALIGNMENT is set to
119
120Similarly, the macro PPC_CACHE_ALIGN_POWER is set to the
121
122@ifinfo
123@node CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features CPU Model Feature Flags
124@end ifinfo
125@subsection Maximum Interrupts
126
127The macro PPC_INTERRUPT_MAX is set to
128
129@ifinfo
130@node CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features CPU Model Feature Flags
131@end ifinfo
132@subsection Has Double Precision Floating Point
133
134The macro PPC_HAS_DOUBLE is set to
135
136@ifinfo
137@node CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features MSR Values, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features CPU Model Feature Flags
138@end ifinfo
139@subsection Critical Interrupts
140
141The macro PPC_HAS_RFCI is set to
142
143@ifinfo
144@node CPU Model Dependent Features MSR Values, CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags
145@end ifinfo
146@subsection MSR Values
147
148The macro PPC_MSR_DISABLE_MASK is set to
149
150The macro PPC_MSR_INITIAL is set to
151
152The macro PPC_MSR_0 is set to
153
154The macro PPC_MSR_1 is set to
155
156The macro PPC_MSR_2 is set to
157
158The macro PPC_MSR_3 is set to
159
160@ifinfo
161@node CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features MSR Values, CPU Model Dependent Features CPU Model Feature Flags
162@end ifinfo
163@subsection FPU Status Control Register Values
164
165The macro PPC_INIT_FPSCR is set to
166
167@ifinfo
168@node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features FPU Status Control Register Values, CPU Model Dependent Features CPU Model Feature Flags
169@end ifinfo
170@subsection Use Multiword Load/Store Instructions
171
172The macro PPC_USE_MULTIPLE is set to
173
174@ifinfo
175@node CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features CPU Model Feature Flags
176@end ifinfo
177@subsection Instruction Cache Size
178
179The macro PPC_I_CACHE is set to
180
181@ifinfo
182@node CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features CPU Model Feature Flags
183@end ifinfo
184@subsection Data Cache Size
185
186The macro PPC_D_CACHE is set to
187
188@ifinfo
189@node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features
190@end ifinfo
191@section CPU Model Implementation Notes
192
193TBD
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