source: rtems/doc/supplements/powerpc/cpumodel.t @ 03c8223

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Last change on this file since 03c8223 was 03c8223, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 31, 1997 at 6:45:32 PM

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1@c
2@c  COPYRIGHT (c) 1988-1996.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@ifinfo
10@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top
11@end ifinfo
12@chapter CPU Model Dependent Features
13@ifinfo
14@menu
15* CPU Model Dependent Features Introduction::
16* CPU Model Dependent Features CPU Model Feature Flags::
17* CPU Model Dependent Features CPU Model Implementation Notes::
18@end menu
19@end ifinfo
20
21@ifinfo
22@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features, CPU Model Dependent Features
23@end ifinfo
24@section Introduction
25
26Microprocessors are generally classified into
27families with a variety of CPU models or implementations within
28that family.  Within a processor family, there is a high level
29of binary compatibility.  This family may be based on either an
30architectural specification or on maintaining compatibility with
31a popular processor.  Recent microprocessor families such as the
32PowerPC, SPARC, and PA-RISC are based on an architectural specification
33which is independent or any particular CPU model or
34implementation.  Older families such as the M68xxx and the iX86
35evolved as the manufacturer strived to produce higher
36performance processor models which maintained binary
37compatibility with older models.
38
39RTEMS takes advantage of the similarity of the
40various models within a CPU family.  Although the models do vary
41in significant ways, the high level of compatibility makes it
42possible to share the bulk of the CPU dependent executive code
43across the entire family.
44
45@ifinfo
46@node CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Introduction, CPU Model Dependent Features
47@end ifinfo
48@section CPU Model Feature Flags
49@ifinfo
50@menu
51* CPU Model Dependent Features CPU Model Name::
52* CPU Model Dependent Features Floating Point Unit::
53* CPU Model Dependent Features Alignment::
54* CPU Model Dependent Features Cache Alignment::
55* CPU Model Dependent Features Maximum Interrupts::
56* CPU Model Dependent Features Has Double Precision Floating Point::
57* CPU Model Dependent Features Critical Interrupts::
58* CPU Model Dependent Features MSR Values::
59* CPU Model Dependent Features Use Multiword Load/Store Instructions::
60* CPU Model Dependent Features Instruction Cache Size::
61* CPU Model Dependent Features Data Cache Size::
62* CPU Model Dependent Features Debug Model::
63* CPU Model Dependent Features Low Power Model::
64@end menu
65@end ifinfo
66
67Each processor family supported by RTEMS has a
68list of features which vary between CPU models
69within a family.  For example, the most common model dependent
70feature regardless of CPU family is the presence or absence of a
71floating point unit or coprocessor.  When defining the list of
72features present on a particular CPU model, one simply notes
73that floating point hardware is or is not present and defines a
74single constant appropriately.  Conditional compilation is
75utilized to include the appropriate source code for this CPU
76model's feature set.  It is important to note that this means
77that RTEMS is thus compiled using the appropriate feature set
78and compilation flags optimal for this CPU model used.  The
79alternative would be to generate a binary which would execute on
80all family members using only the features which were always
81present.
82
83This section presents the set of features which vary
84across PowerPC implementations and are of importance to RTEMS.
85The set of CPU model feature macros are defined in the file
86c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU
87model defined on the compilation command line.
88
89@ifinfo
90@node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags, CPU Model Dependent Features CPU Model Feature Flags
91@end ifinfo
92@subsection CPU Model Name
93
94The macro CPU_MODEL_NAME is a string which designates
95the name of this CPU model.  For example, for the PowerPC 603e
96model, this macro is set to the string "PowerPC 603e".
97
98@ifinfo
99@node CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Alignment, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features CPU Model Feature Flags
100@end ifinfo
101@subsection Floating Point Unit
102
103The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
104has a hardware floating point unit and 0 otherwise.
105
106@ifinfo
107@node CPU Model Dependent Features Alignment, CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features CPU Model Feature Flags
108@end ifinfo
109@subsection Alignment
110
111The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
112requirement for data types on a byte boundary.  This value is used
113to derive the alignment restrictions for memory allocated from
114regions and partitions.
115
116@ifinfo
117@node CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features Alignment, CPU Model Dependent Features CPU Model Feature Flags
118@end ifinfo
119@subsection Cache Alignment
120
121The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache.  It is
122used to align the entry point of critical routines so that as much code
123as possible can be retrieved with the initial read into cache.  This
124is done for the interrupt handler as well as the context switch routines.
125
126In addition, the "shortcut" data structure used by the PowerPC implementation
127to ease access to data elements frequently accessed by RTEMS routines
128implemented in assembly language is aligned using this value.
129
130@ifinfo
131@node CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features Cache Alignment, CPU Model Dependent Features CPU Model Feature Flags
132@end ifinfo
133@subsection Maximum Interrupts
134
135The macro PPC_INTERRUPT_MAX is set to the number of exception sources
136supported by this PowerPC model.
137
138@ifinfo
139@node CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features Maximum Interrupts, CPU Model Dependent Features CPU Model Feature Flags
140@end ifinfo
141@subsection Has Double Precision Floating Point
142
143The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
144has support for double precision floating point numbers.  This is
145important because the floating point registers need only be four bytes
146wide (not eight) if double precision is not supported.
147
148@ifinfo
149@node CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features MSR Values, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features CPU Model Feature Flags
150@end ifinfo
151@subsection Critical Interrupts
152
153The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
154has the Critical Interrupt capability as defined by the IBM 403 models.
155
156@ifinfo
157@node CPU Model Dependent Features MSR Values, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags
158@end ifinfo
159@subsection MSR Values
160
161The macro PPC_MSR_INITIAL is set to
162
163@ifinfo
164@node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features MSR Values, CPU Model Dependent Features CPU Model Feature Flags
165@end ifinfo
166@subsection Use Multiword Load/Store Instructions
167
168The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
169store instructions should be used to perform context switch operations.
170The relative efficiency of multiword load and store instructions versus
171an equivalent set of single word load and store instructions varies based
172upon the PowerPC model.
173
174@ifinfo
175@node CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features CPU Model Feature Flags
176@end ifinfo
177@subsection Instruction Cache Size
178
179The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
180
181@ifinfo
182@node CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features Debug Model, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features CPU Model Feature Flags
183@end ifinfo
184@subsection Data Cache Size
185
186The macro PPC_D_CACHE is set to the size in bytes of the data cache.
187
188@ifinfo
189@node CPU Model Dependent Features Debug Model, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features Data Cache Size, CPU Model Dependent Features CPU Model Feature Flags
190@end ifinfo
191@subsection Debug Model
192
193The macro PPC_DEBUG_MODEL
194
195@table @b
196
197@item @code{PPC_DEBUG_MODEL_STANDARD}
198indicates XXX
199
200@item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY}
201indicates XXX
202
203@item @code{PPC_DEBUG_MODEL_IBM4xx}
204indicates XXX
205
206@end table
207
208@ifinfo
209@node CPU Model Dependent Features Low Power Model, CPU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags
210@end ifinfo
211@subsection Low Power Model
212
213The macro PPC_LOW_POWER_MODE
214
215@table @b
216
217@item @code{PPC_LOW_POWER_MODE_NONE}
218indicates XXX
219
220@item @code{PPC_LOW_POWER_MODE_STANDARD}
221indicates XXX
222
223@end table
224
225
226@ifinfo
227@node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features
228@end ifinfo
229@section CPU Model Implementation Notes
230
231TBD
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