source: rtems/doc/supplements/powerpc/bsp.t @ 563f7e0

4.104.114.84.95
Last change on this file since 563f7e0 was 563f7e0, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 1, 1997 at 6:39:44 PM

New files -- PowerPC supplement is based on the SPARC supplement.
This version has had some initial work done to convert it to
be PowerPC specific.

  • Property mode set to 100644
File size: 3.7 KB
Line 
1@c
2@c  COPYRIGHT (c) 1988-1996.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@ifinfo
10@node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top
11@end ifinfo
12@chapter Board Support Packages
13@ifinfo
14@menu
15* Board Support Packages Introduction::
16* Board Support Packages System Reset::
17* Board Support Packages Processor Initialization::
18@end menu
19@end ifinfo
20
21@ifinfo
22@node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages
23@end ifinfo
24@section Introduction
25
26An RTEMS Board Support Package (BSP) must be designed
27to support a particular processor and target board combination.
28This chapter presents a discussion of SPARC specific BSP issues.
29For more information on developing a BSP, refer to the chapter
30titled Board Support Packages in the RTEMS
31Applications User's Guide.
32
33@ifinfo
34@node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages
35@end ifinfo
36@section System Reset
37
38An RTEMS based application is initiated or
39re-initiated when the SPARC processor is reset.  When the SPARC
40is reset, the processor performs the following actions:
41
42@itemize @bullet
43@item the enable trap (ET) of the psr is set to 0 to disable
44traps,
45
46@item the supervisor bit (S) of the psr is set to 1 to enter
47supervisor mode, and
48
49@item the PC is set 0 and the nPC is set to 4.
50@end itemize
51
52The processor then begins to execute the code at
53location 0.  It is important to note that all fields in the psr
54are not explicitly set by the above steps and all other
55registers retain their value from the previous execution mode.
56This is true even of the Trap Base Register (TBR) whose contents
57reflect the last trap which occurred before the reset.
58
59@ifinfo
60@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
61@end ifinfo
62@section Processor Initialization
63
64It is the responsibility of the application's
65initialization code to initialize the TBR and install trap
66handlers for at least the register window overflow and register
67window underflow conditions.  Traps should be enabled before
68invoking any subroutines to allow for register window
69management.  However, interrupts should be disabled by setting
70the Processor Interrupt Level (pil) field of the psr to 15.
71RTEMS installs it's own Trap Table as part of initialization
72which is initialized with the contents of the Trap Table in
73place when the rtems_initialize_executive directive was invoked.
74Upon completion of executive initialization, interrupts are
75enabled.
76
77If this SPARC implementation supports on-chip caching
78and this is to be utilized, then it should be enabled during the
79reset application initialization code.
80
81In addition to the requirements described in the
82Board Support Packages chapter of the @value{RTEMS-LANGUAGE}
83Applications User's Manual for the reset code
84which is executed before the call to
85rtems_initialize executive, the SPARC version has the following
86specific requirements:
87
88@itemize @bullet
89@item Must leave the S bit of the status register set so that
90the SPARC remains in the supervisor state.
91
92@item Must set stack pointer (sp) such that a minimum stack
93size of MINIMUM_STACK_SIZE bytes is provided for the
94rtems_initialize executive directive.
95
96@item Must disable all external interrupts (i.e. set the pil
97to 15).
98
99@item Must enable traps so window overflow and underflow
100conditions can be properly handled.
101
102@item Must initialize the SPARC's initial trap table with at
103least trap handlers for register window overflow and register
104window underflow.
105@end itemize
106
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