1 | @c |
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2 | @c COPYRIGHT (c) 1988-1999. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @chapter Board Support Packages |
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10 | |
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11 | @section Introduction |
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12 | |
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13 | An RTEMS Board Support Package (BSP) must be designed |
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14 | to support a particular processor and target board combination. |
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15 | This chapter presents a discussion of PowerPC specific BSP issues. |
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16 | For more information on developing a BSP, refer to the chapter |
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17 | titled Board Support Packages in the RTEMS |
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18 | Applications User's Guide. |
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19 | |
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20 | @section System Reset |
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21 | |
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22 | An RTEMS based application is initiated or |
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23 | re-initiated when the PowerPC processor is reset. The PowerPC |
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24 | architecture defines a Reset Exception, but leaves the |
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25 | details of the CPU state as implementation specific. Please |
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26 | refer to the User's Manual for the CPU model in question. |
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27 | |
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28 | In general, at power-up the PowerPC begin execution at address |
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29 | 0xFFF00100 in supervisor mode with all exceptions disabled. For |
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30 | soft resets, the CPU will vector to either 0xFFF00100 or 0x00000100 |
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31 | depending upon the setting of the Exception Prefix bit in the MSR. |
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32 | If during a soft reset, a Machine Check Exception occurs, then the |
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33 | CPU may execute a hard reset. |
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34 | |
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35 | @section Processor Initialization |
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36 | |
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37 | It is the responsibility of the application's |
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38 | initialization code to initialize the CPU and board |
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39 | to a quiescent state before invoking the @code{rtems_initialize_executive} |
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40 | directive. It is recommended that the BSP utilize the @code{predriver_hook} |
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41 | to install default handlers for all exceptions. These default handlers |
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42 | may be overwritten as various device drivers and subsystems install |
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43 | their own exception handlers. Upon completion of RTEMS executive |
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44 | initialization, all interrupts are enabled. |
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45 | |
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46 | If this PowerPC implementation supports on-chip caching |
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47 | and this is to be utilized, then it should be enabled during the |
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48 | reset application initialization code. On-chip caching has been |
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49 | observed to prevent some emulators from working properly, so it |
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50 | may be necessary to run with caching disabled to use these emulators. |
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51 | |
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52 | In addition to the requirements described in the |
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53 | @b{Board Support Packages} chapter of the @b{@value{LANGUAGE} |
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54 | Applications User's Manual} for the reset code |
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55 | which is executed before the call to @code{rtems_initialize_executive}, |
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56 | the PowrePC version has the following specific requirements: |
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57 | |
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58 | @itemize @bullet |
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59 | @item Must leave the PR bit of the Machine State Register (MSR) set |
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60 | to 0 so the PowerPC remains in the supervisor state. |
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61 | |
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62 | @item Must set stack pointer (sp or r1) such that a minimum stack |
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63 | size of MINIMUM_STACK_SIZE bytes is provided for the |
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64 | @code{rtems_initialize_executive} directive. |
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65 | |
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66 | @item Must disable all external interrupts (i.e. clear the EI (EE) |
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67 | bit of the machine state register). |
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68 | |
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69 | @item Must enable traps so window overflow and underflow |
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70 | conditions can be properly handled. |
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71 | |
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72 | @item Must initialize the PowerPC's initial Exception Table with default |
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73 | handlers. |
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74 | |
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75 | @end itemize |
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76 | |
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