source: rtems/doc/supplements/powerpc/bsp.t @ 03c8223

4.104.114.84.95
Last change on this file since 03c8223 was 03c8223, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 31, 1997 at 6:45:32 PM

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1@c
2@c  COPYRIGHT (c) 1988-1996.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@ifinfo
10@node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top
11@end ifinfo
12@chapter Board Support Packages
13@ifinfo
14@menu
15* Board Support Packages Introduction::
16* Board Support Packages System Reset::
17* Board Support Packages Processor Initialization::
18@end menu
19@end ifinfo
20
21@ifinfo
22@node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages
23@end ifinfo
24@section Introduction
25
26An RTEMS Board Support Package (BSP) must be designed
27to support a particular processor and target board combination.
28This chapter presents a discussion of PowerPC specific BSP issues.
29For more information on developing a BSP, refer to the chapter
30titled Board Support Packages in the RTEMS
31Applications User's Guide.
32
33@ifinfo
34@node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages
35@end ifinfo
36@section System Reset
37
38An RTEMS based application is initiated or
39re-initiated when the PowerPC processor is reset.  When the PowerPC
40is reset, the processor performs the following actions:
41
42@itemize @bullet
43@item TBD
44
45@item TBD
46
47@item TBD
48@end itemize
49
50The processor then begins to execute the code at location 0x00100. 
51By using the SRR1 bit corresponding to MSR[RI] the softwere may
52distinguish between power-on reset and other types of system resets.
53
54It is important to note that all fields in the psr
55are not explicitly set by the above steps and all other
56registers retain their value from the previous execution mode.
57This is true even of the Trap Base Register (TBR) whose contents
58reflect the last trap which occurred before the reset.
59
60@ifinfo
61@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
62@end ifinfo
63@section Processor Initialization
64
65It is the responsibility of the application's
66initialization code to initialize the TBR and install trap
67handlers for at least the register window overflow and register
68window underflow conditions.  Traps should be enabled before
69invoking any subroutines to allow for register window
70management.  However, interrupts should be disabled by setting
71the Processor Interrupt Level (pil) field of the psr to 15.
72RTEMS installs it's own Trap Table as part of initialization
73which is initialized with the contents of the Trap Table in
74place when the rtems_initialize_executive directive was invoked.
75Upon completion of executive initialization, interrupts are
76enabled.
77
78If this SPARC implementation supports on-chip caching
79and this is to be utilized, then it should be enabled during the
80reset application initialization code.
81
82In addition to the requirements described in the
83Board Support Packages chapter of the @value{LANGUAGE}
84Applications User's Manual for the reset code
85which is executed before the call to
86rtems_initialize executive, the SPARC version has the following
87specific requirements:
88
89@itemize @bullet
90@item Must leave the S bit of the status register set so that
91the SPARC remains in the supervisor state.
92
93@item Must set stack pointer (sp) such that a minimum stack
94size of MINIMUM_STACK_SIZE bytes is provided for the
95rtems_initialize executive directive.
96
97@item Must disable all external interrupts (i.e. set the pil
98to 15).
99
100@item Must enable traps so window overflow and underflow
101conditions can be properly handled.
102
103@item Must initialize the SPARC's initial trap table with at
104least trap handlers for register window overflow and register
105window underflow.
106@end itemize
107
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