source: rtems/doc/supplements/mips64orion/intr_NOTIMES.t @ f48b1000

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Last change on this file since f48b1000 was f48b1000, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 23, 1998 at 10:09:47 PM

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1@c
2@c  Interrupt Stack Frame Picture
3@c
4@c  COPYRIGHT (c) 1988-1998.
5@c  On-Line Applications Research Corporation (OAR).
6@c  All rights reserved.
7@c
8@c  $Id$
9@c
10
11@chapter Interrupt Processing
12
13@section Introduction
14
15Different types of processors respond to the
16occurrence of an interrupt in its own unique fashion. In
17addition, each processor type provides a control mechanism to
18allow for the proper handling of an interrupt.  The processor
19dependent response to the interrupt modifies the current
20execution state and results in a change in the execution stream.
21Most processors require that an interrupt handler utilize some
22special control mechanisms to return to the normal processing
23stream.  Although RTEMS hides many of the processor dependent
24details of interrupt processing, it is important to understand
25how the RTEMS interrupt manager is mapped onto the processor's
26unique architecture. Discussed in this chapter are the XXX's
27interrupt response and control mechanisms as they pertain to
28RTEMS.
29
30@section Vectoring of an Interrupt Handler
31
32Depending on whether or not the particular CPU
33supports a separate interrupt stack, the XXX family has two
34different interrupt handling models.
35
36@subsection Models Without Separate Interrupt Stacks
37
38Upon receipt of an interrupt the XXX family
39members without separate interrupt stacks automatically perform
40the following actions:
41
42@itemize @bullet
43@item To Be Written
44@end itemize
45
46@subsection Models With Separate Interrupt Stacks
47
48Upon receipt of an interrupt the XXX family
49members with separate interrupt stacks automatically perform the
50following actions:
51
52@itemize @bullet
53@item saves the current status register (SR),
54
55@item clears the master/interrupt (M) bit of the SR to
56indicate the switch from master state to interrupt state,
57
58@item sets the privilege mode to supervisor,
59
60@item suppresses tracing,
61
62@item sets the interrupt mask level equal to the level of the
63interrupt being serviced,
64
65@item pushes an interrupt stack frame (ISF), which includes
66the program counter (PC), the status register (SR), and the
67format/exception vector offset (FVO) word, onto the supervisor
68and interrupt stacks,
69
70@item switches the current stack to the interrupt stack and
71vectors to an interrupt service routine (ISR).  If the ISR was
72installed with the interrupt_catch directive, then the RTEMS
73interrupt handler will begin execution.  The RTEMS interrupt
74handler saves all registers which are not preserved according to
75the calling conventions and invokes the application's ISR.
76@end itemize
77
78A nested interrupt is processed similarly by these
79CPU models with the exception that only a single ISF is placed
80on the interrupt stack and the current stack need not be
81switched.
82
83The FVO word in the Interrupt Stack Frame is examined
84by RTEMS to determine when an outer most interrupt is being
85exited. Since the FVO is used by RTEMS for this purpose, the
86user application code MUST NOT modify this field.
87
88The following shows the Interrupt Stack Frame for
89XXX CPU models with separate interrupt stacks:
90
91@ifset use-ascii
92@example
93@group
94               +----------------------+
95               |    Status Register   | 0x0
96               +----------------------+   
97               | Program Counter High | 0x2
98               +----------------------+   
99               | Program Counter Low  | 0x4
100               +----------------------+   
101               | Format/Vector Offset | 0x6
102               +----------------------+   
103@end group
104@end example
105@end ifset
106
107@ifset use-tex
108@sp 1
109@tex
110\centerline{\vbox{\offinterlineskip\halign{
111\strut\vrule#&
112\hbox to 2.00in{\enskip\hfil#\hfil}&
113\vrule#&
114\hbox to 0.50in{\enskip\hfil#\hfil}
115\cr
116\multispan{3}\hrulefill\cr
117& Status Register && 0x0\cr
118\multispan{3}\hrulefill\cr
119& Program Counter High && 0x2\cr
120\multispan{3}\hrulefill\cr
121& Program Counter Low && 0x4\cr
122\multispan{3}\hrulefill\cr
123& Format/Vector Offset && 0x6\cr
124\multispan{3}\hrulefill\cr
125}}\hfil}
126@end tex
127@end ifset
128
129@ifset use-html
130@html
131<CENTER>
132  <TABLE COLS=2 WIDTH="40%" BORDER=2>
133<TR><TD ALIGN=center><STRONG>Status Register</STRONG></TD>
134    <TD ALIGN=center>0x0</TD></TR>
135<TR><TD ALIGN=center><STRONG>Program Counter High</STRONG></TD>
136    <TD ALIGN=center>0x2</TD></TR>
137<TR><TD ALIGN=center><STRONG>Program Counter Low</STRONG></TD>
138    <TD ALIGN=center>0x4</TD></TR>
139<TR><TD ALIGN=center><STRONG>Format/Vector Offset</STRONG></TD>
140    <TD ALIGN=center>0x6</TD></TR>
141  </TABLE>
142</CENTER>
143@end html
144@end ifset
145
146@section Interrupt Levels
147
148Eight levels (0-7) of interrupt priorities are
149supported by XXX family members with level seven (7) being
150the highest priority.  Level zero (0) indicates that interrupts
151are fully enabled.  Interrupt requests for interrupts with
152priorities less than or equal to the current interrupt mask
153level are ignored.
154
155Although RTEMS supports 256 interrupt levels, the
156XXX family only supports eight.  RTEMS interrupt levels 0
157through 7 directly correspond to XXX interrupt levels.  All
158other RTEMS interrupt levels are undefined and their behavior is
159unpredictable.
160
161@section Disabling of Interrupts by RTEMS
162
163During the execution of directive calls, critical
164sections of code may be executed.  When these sections are
165encountered, RTEMS disables interrupts to level seven (7) before
166the execution of this section and restores them to the previous
167level upon completion of the section.  RTEMS has been optimized
168to insure that interrupts are disabled for less than
169RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
170RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz XXX with
171zero wait states.  These numbers will vary based the
172number of wait states and processor speed present on the target board.
173[NOTE:  The maximum period with interrupts disabled is hand calculated.  This
174calculation was last performed for Release
175RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
176
177Non-maskable interrupts (NMI) cannot be disabled, and
178ISRs which execute at this level MUST NEVER issue RTEMS system
179calls.  If a directive is invoked, unpredictable results may
180occur due to the inability of RTEMS to protect its critical
181sections.  However, ISRs that make no system calls may safely
182execute as non-maskable interrupts.
183
184@section Interrupt Stack
185
186RTEMS allocates the interrupt stack from the
187Workspace Area.  The amount of memory allocated for the
188interrupt stack is determined by the interrupt_stack_size field
189in the CPU Configuration Table.  During the initialization
190process, RTEMS will install its interrupt stack.
191
192The XXX port of RTEMS supports a software managed
193dedicated interrupt stack on those CPU models which do not
194support a separate interrupt stack in hardware.
195
196
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