[f48b1000] | 1 | @c |
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| 2 | @c COPYRIGHT (c) 1988-1998. |
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| 3 | @c On-Line Applications Research Corporation (OAR). |
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| 4 | @c All rights reserved. |
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| 5 | @c |
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| 6 | @c $Id$ |
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| 7 | @c |
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| 8 | |
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| 9 | @chapter Board Support Packages |
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| 10 | |
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| 11 | @section Introduction |
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| 12 | |
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| 13 | An RTEMS Board Support Package (BSP) must be designed |
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| 14 | to support a particular processor and target board combination. |
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| 15 | This chapter presents a discussion of XXX specific BSP |
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| 16 | issues. For more information on developing a BSP, refer to the |
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| 17 | chapter titled Board Support Packages in the RTEMS |
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| 18 | Applications User's Guide. |
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| 19 | |
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| 20 | @section System Reset |
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| 21 | |
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| 22 | An RTEMS based application is initiated or |
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| 23 | re-initiated when the XXX processor is reset. When the |
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| 24 | XXX is reset, the processor performs the following actions: |
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| 25 | |
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| 26 | @itemize @bullet |
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| 27 | @item The tracing bits of the status register are cleared to |
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| 28 | disable tracing. |
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| 29 | |
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| 30 | @item The supervisor interrupt state is entered by setting the |
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| 31 | supervisor (S) bit and clearing the master/interrupt (M) bit of |
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| 32 | the status register. |
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| 33 | |
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| 34 | @item The interrupt mask of the status register is set to |
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| 35 | level 7 to effectively disable all maskable interrupts. |
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| 36 | |
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| 37 | @item The vector base register (VBR) is set to zero. |
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| 38 | |
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| 39 | @item The cache control register (CACR) is set to zero to |
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| 40 | disable and freeze the processor cache. |
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| 41 | |
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| 42 | @item The interrupt stack pointer (ISP) is set to the value |
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| 43 | stored at vector 0 (bytes 0-3) of the exception vector table |
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| 44 | (EVT). |
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| 45 | |
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| 46 | @item The program counter (PC) is set to the value stored at |
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| 47 | vector 1 (bytes 4-7) of the EVT. |
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| 48 | |
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| 49 | @item The processor begins execution at the address stored in |
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| 50 | the PC. |
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| 51 | @end itemize |
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| 52 | |
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| 53 | @section Processor Initialization |
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| 54 | |
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| 55 | The address of the application's initialization code |
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| 56 | should be stored in the first vector of the EVT which will allow |
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| 57 | the immediate vectoring to the application code. If the |
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| 58 | application requires that the VBR be some value besides zero, |
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| 59 | then it should be set to the required value at this point. All |
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| 60 | tasks share the same XXX's VBR value. Because interrupts |
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| 61 | are enabled automatically by RTEMS as part of the initialize |
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| 62 | executive directive, the VBR MUST be set before this directive |
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| 63 | is invoked to insure correct interrupt vectoring. If processor |
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| 64 | caching is to be utilized, then it should be enabled during the |
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| 65 | reset application initialization code. |
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| 66 | |
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| 67 | In addition to the requirements described in the |
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| 68 | Board Support Packages chapter of the Applications User's |
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| 69 | Manual for the reset code which is executed before the call to |
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| 70 | initialize executive, the XXX version has the following |
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| 71 | specific requirements: |
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| 72 | |
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| 73 | @itemize @bullet |
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| 74 | @item Must leave the S bit of the status register set so that |
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| 75 | the XXX remains in the supervisor state. |
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| 76 | |
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| 77 | @item Must set the M bit of the status register to remove the |
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| 78 | XXX from the interrupt state. |
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| 79 | |
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| 80 | @item Must set the master stack pointer (MSP) such that a |
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| 81 | minimum stack size of MINIMUM_STACK_SIZE bytes is provided for |
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| 82 | the initialize executive directive. |
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| 83 | |
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| 84 | @item Must initialize the XXX's vector table. |
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| 85 | @end itemize |
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| 86 | |
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| 87 | Note that the BSP is not responsible for allocating |
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| 88 | or installing the interrupt stack. RTEMS does this |
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| 89 | automatically as part of initialization. If the BSP does not |
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| 90 | install an interrupt stack and -- for whatever reason -- an |
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| 91 | interrupt occurs before initialize_executive is invoked, then |
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| 92 | the results are unpredictable. |
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| 93 | |
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