1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @include common/timemac.texi |
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10 | @tex |
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11 | \global\advance \smallskipamount by -4pt |
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12 | @end tex |
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13 | |
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14 | @ifinfo |
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15 | @node MVME136 Timing Data, MVME136 Timing Data Introduction, Timing Specification Terminology, Top |
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16 | @end ifinfo |
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17 | @chapter MVME136 Timing Data |
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18 | @ifinfo |
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19 | @menu |
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20 | * MVME136 Timing Data Introduction:: |
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21 | * MVME136 Timing Data Hardware Platform:: |
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22 | * MVME136 Timing Data Interrupt Latency:: |
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23 | * MVME136 Timing Data Context Switch:: |
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24 | * MVME136 Timing Data Directive Times:: |
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25 | * MVME136 Timing Data Task Manager:: |
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26 | * MVME136 Timing Data Interrupt Manager:: |
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27 | * MVME136 Timing Data Clock Manager:: |
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28 | * MVME136 Timing Data Timer Manager:: |
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29 | * MVME136 Timing Data Semaphore Manager:: |
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30 | * MVME136 Timing Data Message Manager:: |
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31 | * MVME136 Timing Data Event Manager:: |
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32 | * MVME136 Timing Data Signal Manager:: |
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33 | * MVME136 Timing Data Partition Manager:: |
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34 | * MVME136 Timing Data Region Manager:: |
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35 | * MVME136 Timing Data Dual-Ported Memory Manager:: |
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36 | * MVME136 Timing Data I/O Manager:: |
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37 | * MVME136 Timing Data Rate Monotonic Manager:: |
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38 | @end menu |
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39 | @end ifinfo |
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40 | |
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41 | @ifinfo |
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42 | @node MVME136 Timing Data Introduction, MVME136 Timing Data Hardware Platform, MVME136 Timing Data, MVME136 Timing Data |
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43 | @end ifinfo |
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44 | @section Introduction |
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45 | |
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46 | The timing data for the MC68020 version of RTEMS is |
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47 | provided along with the target dependent aspects concerning the |
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48 | gathering of the timing data. The hardware platform used to |
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49 | gather the times is described to give the reader a better |
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50 | understanding of each directive time provided. Also, provided |
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51 | is a description of the interrupt latency and the context switch |
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52 | times as they pertain to the MC68020 version of RTEMS. |
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53 | |
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54 | @ifinfo |
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55 | @node MVME136 Timing Data Hardware Platform, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Introduction, MVME136 Timing Data |
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56 | @end ifinfo |
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57 | @section Hardware Platform |
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58 | |
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59 | All times reported except for the maximum period |
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60 | interrupts are disabled by RTEMS were measured using a Motorola |
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61 | MVME135 CPU board. The MVME135 is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ |
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62 | Mhz board with one wait |
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63 | state dynamic memory and a MC68881 numeric coprocessor. The |
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64 | Zilog 8036 countdown timer on this board was used to measure |
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65 | elapsed time with a one-half microsecond resolution. All |
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66 | sources of hardware interrupts were disabled, although the |
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67 | interrupt level of the MC68020 allows all interrupts. |
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68 | |
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69 | The maximum period interrupts are disabled was |
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70 | measured by summing the number of CPU cycles required by each |
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71 | assembly language instruction executed while interrupts were |
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72 | disabled. The worst case times of the MC68020 microprocessor |
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73 | were used for each instruction. Zero wait state memory was |
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74 | assumed. The total CPU cycles executed with interrupts |
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75 | disabled, including the instructions to disable and enable |
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76 | interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ |
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77 | Mhz MC68020. It |
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78 | should be noted that the worst case instruction times for the |
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79 | MC68020 assume that the internal cache is disabled and that no |
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80 | instructions overlap. |
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81 | |
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82 | @ifinfo |
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83 | @node MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Context Switch, MVME136 Timing Data Hardware Platform, MVME136 Timing Data |
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84 | @end ifinfo |
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85 | @section Interrupt Latency |
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86 | |
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87 | The maximum period with interrupts disabled within |
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88 | RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD |
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89 | microseconds including the instructions |
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90 | which disable and re-enable interrupts. The time required for |
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91 | the MC68020 to vector an interrupt and for the RTEMS entry |
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92 | overhead before invoking the user's interrupt handler are a |
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93 | total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK |
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94 | microseconds. These combine to yield a worst case |
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95 | interrupt latency of less than |
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96 | RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK |
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97 | microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ |
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98 | Mhz. [NOTE: The maximum period with interrupts |
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99 | disabled was last determined for Release |
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100 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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101 | |
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102 | It should be noted again that the maximum period with |
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103 | interrupts disabled within RTEMS is hand-timed and based upon |
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104 | worst case (i.e. CPU cache disabled and no instruction overlap) |
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105 | times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ |
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106 | Mhz MC68020. The interrupt vector and entry |
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107 | overhead time was generated on an MVME135 benchmark platform |
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108 | using the Multiprocessing Communications registers to generate |
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109 | as the interrupt source. |
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110 | |
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111 | @ifinfo |
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112 | @node MVME136 Timing Data Context Switch, MVME136 Timing Data Directive Times, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data |
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113 | @end ifinfo |
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114 | @section Context Switch |
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115 | |
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116 | The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS |
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117 | microseconds on the MVME135 benchmark platform when no floating |
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118 | point context is saved or restored. Additional execution time |
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119 | is required when a TASK_SWITCH user extension is configured. |
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120 | The use of the TASK_SWITCH extension is application dependent. |
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121 | Thus, its execution time is not considered part of the raw |
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122 | context switch time. |
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123 | |
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124 | Since RTEMS was designed specifically for embedded |
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125 | missile applications which are floating point intensive, the |
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126 | executive is optimized to avoid unnecessarily saving and |
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127 | restoring the state of the numeric coprocessor. The state of |
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128 | the numeric coprocessor is only saved when an FLOATING_POINT |
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129 | task is dispatched and that task was not the last task to |
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130 | utilize the coprocessor. In a system with only one |
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131 | FLOATING_POINT task, the state of the numeric coprocessor will |
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132 | never be saved or restored. When the first FLOATING_POINT task |
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133 | is dispatched, RTEMS does not need to save the current state of |
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134 | the numeric coprocessor. |
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135 | |
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136 | The exact amount of time required to save and restore |
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137 | floating point context is dependent on whether an MC68881 or |
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138 | MC68882 is being used as well as the state of the numeric |
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139 | coprocessor. These numeric coprocessors define three operating |
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140 | states: initialized, idle, and busy. RTEMS places the |
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141 | coprocessor in the initialized state when a task is started or |
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142 | restarted. Once the task has utilized the coprocessor, it is in |
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143 | the idle state when floating point instructions are not |
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144 | executing and the busy state when floating point instructions |
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145 | are executing. The state of the coprocessor is task specific. |
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146 | |
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147 | The following table summarizes the context switch |
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148 | times for the MVME135 benchmark platform: |
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149 | |
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150 | @include timetbl.texi |
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151 | |
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152 | @tex |
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153 | \global\advance \smallskipamount by 4pt |
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154 | @end tex |
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