source: rtems/doc/supplements/m68k/timedata.t @ 1e524995

4.104.114.84.95
Last change on this file since 1e524995 was 1e524995, checked in by Joel Sherrill <joel.sherrill@…>, on 02/06/98 at 14:14:30

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1@c
2@c  COPYRIGHT (c) 1988-1998.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@include ../common/timemac.texi
10@tex
11\global\advance \smallskipamount by -4pt
12@end tex
13
14@ifinfo
15@node MC68020 Timing Data, MC68020 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
16@end ifinfo
17@chapter MC68020 Timing Data
18@ifinfo
19@menu
20* MC68020 Timing Data Introduction::
21* MC68020 Timing Data Hardware Platform::
22* MC68020 Timing Data Interrupt Latency::
23* MC68020 Timing Data Context Switch::
24* MC68020 Timing Data Directive Times::
25* MC68020 Timing Data Task Manager::
26* MC68020 Timing Data Interrupt Manager::
27* MC68020 Timing Data Clock Manager::
28* MC68020 Timing Data Timer Manager::
29* MC68020 Timing Data Semaphore Manager::
30* MC68020 Timing Data Message Manager::
31* MC68020 Timing Data Event Manager::
32* MC68020 Timing Data Signal Manager::
33* MC68020 Timing Data Partition Manager::
34* MC68020 Timing Data Region Manager::
35* MC68020 Timing Data Dual-Ported Memory Manager::
36* MC68020 Timing Data I/O Manager::
37* MC68020 Timing Data Rate Monotonic Manager::
38@end menu
39@end ifinfo
40
41@ifinfo
42@node MC68020 Timing Data Introduction, MC68020 Timing Data Hardware Platform, MC68020 Timing Data, MC68020 Timing Data
43@end ifinfo
44@section Introduction
45
46The timing data for the MC68020 version of RTEMS is
47provided along with the target dependent aspects concerning the
48gathering of the timing data.  The hardware platform used to
49gather the times is described to give the reader a better
50understanding of each directive time provided.  Also, provided
51is a description of the interrupt latency and the context switch
52times as they pertain to the MC68020 version of RTEMS.
53
54@ifinfo
55@node MC68020 Timing Data Hardware Platform, MC68020 Timing Data Interrupt Latency, MC68020 Timing Data Introduction, MC68020 Timing Data
56@end ifinfo
57@section Hardware Platform
58
59All times reported except for the maximum period
60interrupts are disabled by RTEMS were measured using a Motorola
61MVME135 CPU board.  The MVME135 is a 20Mhz board with one wait
62state dynamic memory and a MC68881 numeric coprocessor.  The
63Zilog 8036 countdown timer on this board was used to measure
64elapsed time with a one-half microsecond resolution.  All
65sources of hardware interrupts were disabled, although the
66interrupt level of the MC68020 allows all interrupts.
67
68The maximum period interrupts are disabled was
69measured by summing the number of CPU cycles required by each
70assembly language instruction executed while interrupts were
71disabled.  The worst case times of the MC68020 microprocessor
72were used for each instruction.  Zero wait state memory was
73assumed.  The total CPU cycles executed with interrupts
74disabled, including the instructions to disable and enable
75interrupts, was divided by 20 to simulate a 20Mhz MC68020.  It
76should be noted that the worst case instruction times for the
77MC68020 assume that the internal cache is disabled and that no
78instructions overlap.
79
80@ifinfo
81@node MC68020 Timing Data Interrupt Latency, MC68020 Timing Data Context Switch, MC68020 Timing Data Hardware Platform, MC68020 Timing Data
82@end ifinfo
83@section Interrupt Latency
84
85The maximum period with interrupts disabled within
86RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD
87microseconds including the instructions
88which disable and re-enable interrupts.  The time required for
89the MC68020 to vector an interrupt and for the RTEMS entry
90overhead before invoking the user's interrupt handler are a
91total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
92microseconds.  These combine to yield a worst case
93interrupt latency of less than
94RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
95microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
96disabled was last determined for Release
97RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
98
99It should be noted again that the maximum period with
100interrupts disabled within RTEMS is hand-timed and based upon
101worst case (i.e. CPU cache disabled and no instruction overlap)
102times for a 20Mhz MC68020.  The interrupt vector and entry
103overhead time was generated on an MVME135 benchmark platform
104using the Multiprocessing Communications registers to generate
105as the interrupt source.
106
107@ifinfo
108@node MC68020 Timing Data Context Switch, MC68020 Timing Data Directive Times, MC68020 Timing Data Interrupt Latency, MC68020 Timing Data
109@end ifinfo
110@section Context Switch
111
112The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
113microseconds on the MVME135 benchmark platform when no floating
114point context is saved or restored.  Additional execution time
115is required when a TASK_SWITCH user extension is configured.
116The use of the TASK_SWITCH extension is application dependent.
117Thus, its execution time is not considered part of the raw
118context switch time.
119
120Since RTEMS was designed specifically for embedded
121missile applications which are floating point intensive, the
122executive is optimized to avoid unnecessarily saving and
123restoring the state of the numeric coprocessor.  The state of
124the numeric coprocessor is only saved when an FLOATING_POINT
125task is dispatched and that task was not the last task to
126utilize the coprocessor.  In a system with only one
127FLOATING_POINT task, the state of the numeric coprocessor will
128never be saved or restored.  When the first FLOATING_POINT task
129is dispatched, RTEMS does not need to save the current state of
130the numeric coprocessor.
131
132The exact amount of time required to save and restore
133floating point context is dependent on whether an MC68881 or
134MC68882 is being used as well as the state of the numeric
135coprocessor.  These numeric coprocessors define three operating
136states: initialized, idle, and busy.  RTEMS places the
137coprocessor in the initialized state when a task is started or
138restarted.  Once the task has utilized the coprocessor, it is in
139the idle state when floating point instructions are not
140executing and the busy state when floating point instructions
141are executing.  The state of the coprocessor is task specific.
142
143The following table summarizes the context switch
144times for the MVME135 benchmark platform:
145
146@include timetbl.texi
147
148@tex
149\global\advance \smallskipamount by 4pt
150@end tex
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