1 | @c |
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2 | @c Interrupt Stack Frame Picture |
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3 | @c |
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4 | @c COPYRIGHT (c) 1988-1997. |
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5 | @c On-Line Applications Research Corporation (OAR). |
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6 | @c All rights reserved. |
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7 | @c |
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8 | @c $Id$ |
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9 | @c |
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10 | |
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11 | @ifinfo |
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12 | @node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top |
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13 | @end ifinfo |
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14 | @chapter Interrupt Processing |
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15 | @ifinfo |
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16 | @menu |
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17 | * Interrupt Processing Introduction:: |
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18 | * Interrupt Processing Vectoring of an Interrupt Handler:: |
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19 | * Interrupt Processing Interrupt Levels:: |
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20 | * Interrupt Processing Disabling of Interrupts by RTEMS:: |
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21 | * Interrupt Processing Interrupt Stack:: |
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22 | @end menu |
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23 | @end ifinfo |
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24 | |
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25 | @ifinfo |
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26 | @node Interrupt Processing Introduction, Interrupt Processing Vectoring of an Interrupt Handler, Interrupt Processing, Interrupt Processing |
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27 | @end ifinfo |
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28 | @section Introduction |
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29 | |
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30 | Different types of processors respond to the |
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31 | occurrence of an interrupt in its own unique fashion. In |
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32 | addition, each processor type provides a control mechanism to |
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33 | allow for the proper handling of an interrupt. The processor |
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34 | dependent response to the interrupt modifies the current |
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35 | execution state and results in a change in the execution stream. |
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36 | Most processors require that an interrupt handler utilize some |
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37 | special control mechanisms to return to the normal processing |
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38 | stream. Although RTEMS hides many of the processor dependent |
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39 | details of interrupt processing, it is important to understand |
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40 | how the RTEMS interrupt manager is mapped onto the processor's |
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41 | unique architecture. Discussed in this chapter are the MC68xxx's |
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42 | interrupt response and control mechanisms as they pertain to |
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43 | RTEMS. |
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44 | |
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45 | @ifinfo |
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46 | @node Interrupt Processing Vectoring of an Interrupt Handler, Models Without Separate Interrupt Stacks, Interrupt Processing Introduction, Interrupt Processing |
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47 | @end ifinfo |
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48 | @section Vectoring of an Interrupt Handler |
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49 | @ifinfo |
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50 | @menu |
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51 | * Models Without Separate Interrupt Stacks:: |
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52 | * Models With Separate Interrupt Stacks:: |
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53 | @end menu |
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54 | @end ifinfo |
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55 | |
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56 | Depending on whether or not the particular CPU |
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57 | supports a separate interrupt stack, the MC68xxx family has two |
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58 | different interrupt handling models. |
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59 | |
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60 | @ifinfo |
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61 | @node Models Without Separate Interrupt Stacks, Models With Separate Interrupt Stacks, Interrupt Processing Vectoring of an Interrupt Handler, Interrupt Processing Vectoring of an Interrupt Handler |
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62 | @end ifinfo |
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63 | @subsection Models Without Separate Interrupt Stacks |
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64 | |
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65 | Upon receipt of an interrupt the MC68xxx family |
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66 | members without separate interrupt stacks automatically perform |
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67 | the following actions: |
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68 | |
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69 | @itemize @bullet |
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70 | @item To Be Written |
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71 | @end itemize |
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72 | |
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73 | @ifinfo |
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74 | @node Models With Separate Interrupt Stacks, Interrupt Processing Interrupt Levels, Models Without Separate Interrupt Stacks, Interrupt Processing Vectoring of an Interrupt Handler |
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75 | @end ifinfo |
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76 | @subsection Models With Separate Interrupt Stacks |
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77 | |
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78 | Upon receipt of an interrupt the MC68xxx family |
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79 | members with separate interrupt stacks automatically perform the |
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80 | following actions: |
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81 | |
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82 | @itemize @bullet |
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83 | @item saves the current status register (SR), |
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84 | |
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85 | @item clears the master/interrupt (M) bit of the SR to |
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86 | indicate the switch from master state to interrupt state, |
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87 | |
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88 | @item sets the privilege mode to supervisor, |
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89 | |
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90 | @item suppresses tracing, |
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91 | |
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92 | @item sets the interrupt mask level equal to the level of the |
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93 | interrupt being serviced, |
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94 | |
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95 | @item pushes an interrupt stack frame (ISF), which includes |
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96 | the program counter (PC), the status register (SR), and the |
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97 | format/exception vector offset (FVO) word, onto the supervisor |
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98 | and interrupt stacks, |
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99 | |
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100 | @item switches the current stack to the interrupt stack and |
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101 | vectors to an interrupt service routine (ISR). If the ISR was |
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102 | installed with the interrupt_catch directive, then the RTEMS |
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103 | interrupt handler will begin execution. The RTEMS interrupt |
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104 | handler saves all registers which are not preserved according to |
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105 | the calling conventions and invokes the application's ISR. |
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106 | @end itemize |
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107 | |
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108 | A nested interrupt is processed similarly by these |
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109 | CPU models with the exception that only a single ISF is placed |
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110 | on the interrupt stack and the current stack need not be |
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111 | switched. |
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112 | |
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113 | The FVO word in the Interrupt Stack Frame is examined |
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114 | by RTEMS to determine when an outer most interrupt is being |
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115 | exited. Since the FVO is used by RTEMS for this purpose, the |
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116 | user application code MUST NOT modify this field. |
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117 | |
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118 | The following shows the Interrupt Stack Frame for |
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119 | MC68xxx CPU models with separate interrupt stacks: |
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120 | |
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121 | @ifset use-ascii |
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122 | @example |
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123 | @group |
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124 | +----------------------+ |
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125 | | Status Register | 0x0 |
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126 | +----------------------+ |
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127 | | Program Counter High | 0x2 |
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128 | +----------------------+ |
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129 | | Program Counter Low | 0x4 |
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130 | +----------------------+ |
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131 | | Format/Vector Offset | 0x6 |
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132 | +----------------------+ |
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133 | @end group |
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134 | @end example |
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135 | @end ifset |
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136 | |
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137 | @ifset use-tex |
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138 | @sp 1 |
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139 | @tex |
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140 | \centerline{\vbox{\offinterlineskip\halign{ |
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141 | \strut\vrule#& |
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142 | \hbox to 2.00in{\enskip\hfil#\hfil}& |
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143 | \vrule#& |
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144 | \hbox to 0.50in{\enskip\hfil#\hfil} |
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145 | \cr |
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146 | \multispan{3}\hrulefill\cr |
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147 | & Status Register && 0x0\cr |
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148 | \multispan{3}\hrulefill\cr |
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149 | & Program Counter High && 0x2\cr |
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150 | \multispan{3}\hrulefill\cr |
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151 | & Program Counter Low && 0x4\cr |
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152 | \multispan{3}\hrulefill\cr |
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153 | & Format/Vector Offset && 0x6\cr |
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154 | \multispan{3}\hrulefill\cr |
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155 | }}\hfil} |
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156 | @end tex |
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157 | @end ifset |
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158 | |
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159 | @ifset use-html |
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160 | @html |
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161 | <CENTER> |
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162 | <TABLE COLS=2 WIDTH="40%" BORDER=2> |
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163 | <TR><TD ALIGN=center><STRONG>Status Register</STRONG></TD> |
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164 | <TD ALIGN=center>0x0</TD></TR> |
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165 | <TR><TD ALIGN=center><STRONG>Program Counter High</STRONG></TD> |
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166 | <TD ALIGN=center>0x2</TD></TR> |
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167 | <TR><TD ALIGN=center><STRONG>Program Counter Low</STRONG></TD> |
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168 | <TD ALIGN=center>0x4</TD></TR> |
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169 | <TR><TD ALIGN=center><STRONG>Format/Vector Offset</STRONG></TD> |
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170 | <TD ALIGN=center>0x6</TD></TR> |
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171 | </TABLE> |
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172 | </CENTER> |
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173 | @end html |
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174 | @end ifset |
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175 | |
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176 | @ifinfo |
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177 | @node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Models With Separate Interrupt Stacks, Interrupt Processing |
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178 | @end ifinfo |
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179 | @section Interrupt Levels |
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180 | |
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181 | Eight levels (0-7) of interrupt priorities are |
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182 | supported by MC68xxx family members with level seven (7) being |
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183 | the highest priority. Level zero (0) indicates that interrupts |
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184 | are fully enabled. Interrupt requests for interrupts with |
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185 | priorities less than or equal to the current interrupt mask |
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186 | level are ignored. |
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187 | |
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188 | Although RTEMS supports 256 interrupt levels, the |
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189 | MC68xxx family only supports eight. RTEMS interrupt levels 0 |
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190 | through 7 directly correspond to MC68xxx interrupt levels. All |
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191 | other RTEMS interrupt levels are undefined and their behavior is |
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192 | unpredictable. |
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193 | |
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194 | @ifinfo |
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195 | @node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing |
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196 | @end ifinfo |
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197 | @section Disabling of Interrupts by RTEMS |
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198 | |
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199 | During the execution of directive calls, critical |
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200 | sections of code may be executed. When these sections are |
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201 | encountered, RTEMS disables interrupts to level seven (7) before |
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202 | the execution of this section and restores them to the previous |
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203 | level upon completion of the section. RTEMS has been optimized |
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204 | to insure that interrupts are disabled for less than |
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205 | RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a |
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206 | RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz MC68020 with |
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207 | zero wait states. These numbers will vary based the |
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208 | number of wait states and processor speed present on the target board. |
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209 | [NOTE: The maximum period with interrupts disabled is hand calculated. This |
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210 | calculation was last performed for Release |
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211 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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212 | |
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213 | Non-maskable interrupts (NMI) cannot be disabled, and |
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214 | ISRs which execute at this level MUST NEVER issue RTEMS system |
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215 | calls. If a directive is invoked, unpredictable results may |
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216 | occur due to the inability of RTEMS to protect its critical |
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217 | sections. However, ISRs that make no system calls may safely |
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218 | execute as non-maskable interrupts. |
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219 | |
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220 | @ifinfo |
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221 | @node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing |
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222 | @end ifinfo |
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223 | @section Interrupt Stack |
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224 | |
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225 | RTEMS allocates the interrupt stack from the |
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226 | Workspace Area. The amount of memory allocated for the |
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227 | interrupt stack is determined by the interrupt_stack_size field |
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228 | in the CPU Configuration Table. During the initialization |
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229 | process, RTEMS will install its interrupt stack. |
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230 | |
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231 | The MC68xxx port of RTEMS supports a software managed |
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232 | dedicated interrupt stack on those CPU models which do not |
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233 | support a separate interrupt stack in hardware. |
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234 | |
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235 | |
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