source: rtems/doc/supplements/m68k/intr_NOTIMES.t @ 139b2e4a

4.104.114.84.95
Last change on this file since 139b2e4a was 139b2e4a, checked in by Joel Sherrill <joel.sherrill@…>, on 06/04/97 at 18:32:07

added CVS Id string

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1@c
2@c  Interrupt Stack Frame Picture
3@c
4@c  COPYRIGHT (c) 1988-1997.
5@c  On-Line Applications Research Corporation (OAR).
6@c  All rights reserved.
7@c
8@c  $Id$
9@c
10
11@ifinfo
12@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top
13@end ifinfo
14@chapter Interrupt Processing
15@ifinfo
16@menu
17* Interrupt Processing Introduction::
18* Interrupt Processing Vectoring of an Interrupt Handler::
19* Interrupt Processing Interrupt Levels::
20* Interrupt Processing Disabling of Interrupts by RTEMS::
21* Interrupt Processing Interrupt Stack::
22@end menu
23@end ifinfo
24
25@ifinfo
26@node Interrupt Processing Introduction, Interrupt Processing Vectoring of an Interrupt Handler, Interrupt Processing, Interrupt Processing
27@end ifinfo
28@section Introduction
29
30Different types of processors respond to the
31occurrence of an interrupt in its own unique fashion. In
32addition, each processor type provides a control mechanism to
33allow for the proper handling of an interrupt.  The processor
34dependent response to the interrupt modifies the current
35execution state and results in a change in the execution stream.
36Most processors require that an interrupt handler utilize some
37special control mechanisms to return to the normal processing
38stream.  Although RTEMS hides many of the processor dependent
39details of interrupt processing, it is important to understand
40how the RTEMS interrupt manager is mapped onto the processor's
41unique architecture. Discussed in this chapter are the MC68xxx's
42interrupt response and control mechanisms as they pertain to
43RTEMS.
44
45@ifinfo
46@node Interrupt Processing Vectoring of an Interrupt Handler, Models Without Separate Interrupt Stacks, Interrupt Processing Introduction, Interrupt Processing
47@end ifinfo
48@section Vectoring of an Interrupt Handler
49@ifinfo
50@menu
51* Models Without Separate Interrupt Stacks::
52* Models With Separate Interrupt Stacks::
53@end menu
54@end ifinfo
55
56Depending on whether or not the particular CPU
57supports a separate interrupt stack, the MC68xxx family has two
58different interrupt handling models.
59
60@ifinfo
61@node Models Without Separate Interrupt Stacks, Models With Separate Interrupt Stacks, Interrupt Processing Vectoring of an Interrupt Handler, Interrupt Processing Vectoring of an Interrupt Handler
62@end ifinfo
63@subsection Models Without Separate Interrupt Stacks
64
65Upon receipt of an interrupt the MC68xxx family
66members without separate interrupt stacks automatically perform
67the following actions:
68
69@itemize @bullet
70@item To Be Written
71@end itemize
72
73@ifinfo
74@node Models With Separate Interrupt Stacks, Interrupt Processing Interrupt Levels, Models Without Separate Interrupt Stacks, Interrupt Processing Vectoring of an Interrupt Handler
75@end ifinfo
76@subsection Models With Separate Interrupt Stacks
77
78Upon receipt of an interrupt the MC68xxx family
79members with separate interrupt stacks automatically perform the
80following actions:
81
82@itemize @bullet
83@item saves the current status register (SR),
84
85@item clears the master/interrupt (M) bit of the SR to
86indicate the switch from master state to interrupt state,
87
88@item sets the privilege mode to supervisor,
89
90@item suppresses tracing,
91
92@item sets the interrupt mask level equal to the level of the
93interrupt being serviced,
94
95@item pushes an interrupt stack frame (ISF), which includes
96the program counter (PC), the status register (SR), and the
97format/exception vector offset (FVO) word, onto the supervisor
98and interrupt stacks,
99
100@item switches the current stack to the interrupt stack and
101vectors to an interrupt service routine (ISR).  If the ISR was
102installed with the interrupt_catch directive, then the RTEMS
103interrupt handler will begin execution.  The RTEMS interrupt
104handler saves all registers which are not preserved according to
105the calling conventions and invokes the application's ISR.
106@end itemize
107
108A nested interrupt is processed similarly by these
109CPU models with the exception that only a single ISF is placed
110on the interrupt stack and the current stack need not be
111switched.
112
113The FVO word in the Interrupt Stack Frame is examined
114by RTEMS to determine when an outer most interrupt is being
115exited. Since the FVO is used by RTEMS for this purpose, the
116user application code MUST NOT modify this field.
117
118The following shows the Interrupt Stack Frame for
119MC68xxx CPU models with separate interrupt stacks:
120
121@ifset use-ascii
122@example
123@group
124               +----------------------+
125               |    Status Register   | 0x0
126               +----------------------+   
127               | Program Counter High | 0x2
128               +----------------------+   
129               | Program Counter Low  | 0x4
130               +----------------------+   
131               | Format/Vector Offset | 0x6
132               +----------------------+   
133@end group
134@end example
135@end ifset
136
137@ifset use-tex
138@sp 1
139@tex
140\centerline{\vbox{\offinterlineskip\halign{
141\strut\vrule#&
142\hbox to 2.00in{\enskip\hfil#\hfil}&
143\vrule#&
144\hbox to 0.50in{\enskip\hfil#\hfil}
145\cr
146\multispan{3}\hrulefill\cr
147& Status Register && 0x0\cr
148\multispan{3}\hrulefill\cr
149& Program Counter High && 0x2\cr
150\multispan{3}\hrulefill\cr
151& Program Counter Low && 0x4\cr
152\multispan{3}\hrulefill\cr
153& Format/Vector Offset && 0x6\cr
154\multispan{3}\hrulefill\cr
155}}\hfil}
156@end tex
157@end ifset
158
159@ifset use-html
160@html
161<CENTER>
162  <TABLE COLS=2 WIDTH="40%" BORDER=2>
163<TR><TD ALIGN=center><STRONG>Status Register</STRONG></TD>
164    <TD ALIGN=center>0x0</TD></TR>
165<TR><TD ALIGN=center><STRONG>Program Counter High</STRONG></TD>
166    <TD ALIGN=center>0x2</TD></TR>
167<TR><TD ALIGN=center><STRONG>Program Counter Low</STRONG></TD>
168    <TD ALIGN=center>0x4</TD></TR>
169<TR><TD ALIGN=center><STRONG>Format/Vector Offset</STRONG></TD>
170    <TD ALIGN=center>0x6</TD></TR>
171  </TABLE>
172</CENTER>
173@end html
174@end ifset
175
176@ifinfo
177@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Models With Separate Interrupt Stacks, Interrupt Processing
178@end ifinfo
179@section Interrupt Levels
180
181Eight levels (0-7) of interrupt priorities are
182supported by MC68xxx family members with level seven (7) being
183the highest priority.  Level zero (0) indicates that interrupts
184are fully enabled.  Interrupt requests for interrupts with
185priorities less than or equal to the current interrupt mask
186level are ignored.
187
188Although RTEMS supports 256 interrupt levels, the
189MC68xxx family only supports eight.  RTEMS interrupt levels 0
190through 7 directly correspond to MC68xxx interrupt levels.  All
191other RTEMS interrupt levels are undefined and their behavior is
192unpredictable.
193
194@ifinfo
195@node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing
196@end ifinfo
197@section Disabling of Interrupts by RTEMS
198
199During the execution of directive calls, critical
200sections of code may be executed.  When these sections are
201encountered, RTEMS disables interrupts to level seven (7) before
202the execution of this section and restores them to the previous
203level upon completion of the section.  RTEMS has been optimized
204to insure that interrupts are disabled for less than
205RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
206RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz MC68020 with
207zero wait states.  These numbers will vary based the
208number of wait states and processor speed present on the target board.
209[NOTE:  The maximum period with interrupts disabled is hand calculated.  This
210calculation was last performed for Release
211RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
212
213Non-maskable interrupts (NMI) cannot be disabled, and
214ISRs which execute at this level MUST NEVER issue RTEMS system
215calls.  If a directive is invoked, unpredictable results may
216occur due to the inability of RTEMS to protect its critical
217sections.  However, ISRs that make no system calls may safely
218execute as non-maskable interrupts.
219
220@ifinfo
221@node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing
222@end ifinfo
223@section Interrupt Stack
224
225RTEMS allocates the interrupt stack from the
226Workspace Area.  The amount of memory allocated for the
227interrupt stack is determined by the interrupt_stack_size field
228in the CPU Configuration Table.  During the initialization
229process, RTEMS will install its interrupt stack.
230
231The MC68xxx port of RTEMS supports a software managed
232dedicated interrupt stack on those CPU models which do not
233support a separate interrupt stack in hardware.
234
235
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