1 | @c |
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2 | @c COPYRIGHT (c) 1988-1998. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top |
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11 | @end ifinfo |
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12 | @chapter CPU Model Dependent Features |
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13 | @ifinfo |
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14 | @menu |
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15 | * CPU Model Dependent Features Introduction:: |
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16 | * CPU Model Dependent Features CPU Model Name:: |
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17 | * CPU Model Dependent Features Floating Point Unit:: |
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18 | * CPU Model Dependent Features BFFFO Instruction:: |
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19 | * CPU Model Dependent Features Vector Base Register:: |
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20 | * CPU Model Dependent Features Separate Stacks:: |
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21 | * CPU Model Dependent Features Pre-Indexing Address Mode:: |
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22 | * CPU Model Dependent Features Extend Byte to Long Instruction:: |
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23 | @end menu |
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24 | @end ifinfo |
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25 | |
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26 | @ifinfo |
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27 | @node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features, CPU Model Dependent Features |
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28 | @end ifinfo |
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29 | @section Introduction |
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30 | |
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31 | Microprocessors are generally classified into |
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32 | families with a variety of CPU models or implementations within |
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33 | that family. Within a processor family, there is a high level |
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34 | of binary compatibility. This family may be based on either an |
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35 | architectural specification or on maintaining compatibility with |
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36 | a popular processor. Recent microprocessor families such as the |
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37 | SPARC or PA-RISC are based on an architectural specification |
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38 | which is independent or any particular CPU model or |
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39 | implementation. Older families such as the M68xxx and the iX86 |
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40 | evolved as the manufacturer strived to produce higher |
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41 | performance processor models which maintained binary |
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42 | compatibility with older models. |
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43 | |
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44 | RTEMS takes advantage of the similarity of the |
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45 | various models within a CPU family. Although the models do vary |
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46 | in significant ways, the high level of compatibility makes it |
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47 | possible to share the bulk of the CPU dependent executive code |
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48 | across the entire family. Each processor family supported by |
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49 | RTEMS has a list of features which vary between CPU models |
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50 | within a family. For example, the most common model dependent |
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51 | feature regardless of CPU family is the presence or absence of a |
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52 | floating point unit or coprocessor. When defining the list of |
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53 | features present on a particular CPU model, one simply notes |
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54 | that floating point hardware is or is not present and defines a |
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55 | single constant appropriately. Conditional compilation is |
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56 | utilized to include the appropriate source code for this CPU |
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57 | model's feature set. It is important to note that this means |
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58 | that RTEMS is thus compiled using the appropriate feature set |
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59 | and compilation flags optimal for this CPU model used. The |
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60 | alternative would be to generate a binary which would execute on |
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61 | all family members using only the features which were always |
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62 | present. |
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63 | |
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64 | This chapter presents the set of features which vary |
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65 | across SPARC implementations and are of importance to RTEMS. |
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66 | The set of CPU model feature macros are defined in the file |
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67 | c/src/exec/score/cpu/m68k/m68k.h based upon the particular CPU |
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68 | model defined on the compilation command line. |
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69 | |
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70 | @ifinfo |
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71 | @node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Introduction, CPU Model Dependent Features |
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72 | @end ifinfo |
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73 | @section CPU Model Name |
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74 | |
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75 | The macro CPU_MODEL_NAME is a string which designates |
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76 | the name of this CPU model. For example, for the MC68020 |
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77 | processor, this macro is set to the string "mc68020". |
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78 | |
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79 | @ifinfo |
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80 | @node CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features |
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81 | @end ifinfo |
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82 | @section Floating Point Unit |
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83 | |
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84 | The macro M68K_HAS_FPU is set to 1 to indicate that |
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85 | this CPU model has a hardware floating point unit and 0 |
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86 | otherwise. It does not matter whether the hardware floating |
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87 | point support is incorporated on-chip or is an external |
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88 | coprocessor. |
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89 | |
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90 | @ifinfo |
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91 | @node CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features |
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92 | @end ifinfo |
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93 | @section BFFFO Instruction |
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94 | |
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95 | The macro M68K_HAS_BFFFO is set to 1 to indicate that |
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96 | this CPU model has the bfffo instruction. |
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97 | |
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98 | @ifinfo |
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99 | @node CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features |
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100 | @end ifinfo |
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101 | @section Vector Base Register |
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102 | |
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103 | The macro M68K_HAS_VBR is set to 1 to indicate that |
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104 | this CPU model has a vector base register (vbr). |
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105 | |
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106 | @ifinfo |
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107 | @node CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features |
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108 | @end ifinfo |
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109 | @section Separate Stacks |
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110 | |
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111 | The macro M68K_HAS_SEPARATE_STACKS is set to 1 to |
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112 | indicate that this CPU model has separate interrupt, user, and |
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113 | supervisor mode stacks. |
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114 | |
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115 | @ifinfo |
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116 | @node CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features Extend Byte to Long Instruction, CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features |
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117 | @end ifinfo |
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118 | @section Pre-Indexing Address Mode |
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119 | |
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120 | The macro M68K_HAS_PREINDEXING is set to 1 to indicate that |
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121 | this CPU model has the pre-indexing address mode. |
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122 | |
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123 | @ifinfo |
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124 | @node CPU Model Dependent Features Extend Byte to Long Instruction, Calling Conventions, CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features |
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125 | @end ifinfo |
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126 | @section Extend Byte to Long Instruction |
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127 | |
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128 | The macro M68K_HAS_EXTB_L is set to 1 to indicate that this CPU model |
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129 | has the extb.l instruction. This instruction is supposed to be available |
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130 | in all models based on the cpu32 core as well as mc68020 and up models. |
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