1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @include common/timemac.texi |
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10 | @tex |
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11 | \global\advance \smallskipamount by -4pt |
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12 | @end tex |
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13 | |
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14 | @chapter CVME961 Timing Data |
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15 | |
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16 | NOTE: The CVME961 board used by the RTEMS Project to |
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17 | obtain i960CA times is currently broken. The information in |
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18 | this chapter was obtained using Release 3.2.1. |
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19 | |
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20 | @section Introduction |
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21 | |
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22 | The timing data for the i960CA version of RTEMS is |
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23 | provided along with the target dependent aspects concerning the |
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24 | gathering of the timing data. The hardware platform used to |
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25 | gather the times is described to give the reader a better |
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26 | understanding of each directive time provided. Also, provided |
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27 | is a description of the interrupt latency and the context |
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28 | switch times as they pertain to the i960CA version of RTEMS. |
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29 | |
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30 | @section Hardware Platform |
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31 | |
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32 | All times reported except for the maximum period |
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33 | interrupts are disabled by RTEMS were measured using a Cyclone |
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34 | Microsystems CVME961 board. The CVME961 is a 33 Mhz board with |
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35 | dynamic RAM which has two wait state dynamic memory (four CPU |
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36 | cycles) for read accesses and one wait state (two CPU cycles) |
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37 | for write accesses. The Z8536 on a SQUALL SQSIO4 mezzanine |
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38 | board was used to measure elapsed time with one-half microsecond |
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39 | resolution. All sources of hardware interrupts are disabled, |
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40 | although the interrupt level of the i960CA allows all interrupts. |
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41 | |
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42 | The maximum interrupt disable period was measured by |
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43 | summing the number of CPU cycles required by each assembly |
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44 | language instruction executed while interrupts were disabled. |
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45 | Zero wait state memory was assumed. The total CPU cycles |
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46 | executed with interrupts disabled, including the instructions to |
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47 | disable and enable interrupts, was divided by 33 to simulate a |
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48 | i960CA executing at 33 Mhz with zero wait states. |
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49 | |
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50 | @section Interrupt Latency |
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51 | |
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52 | The maximum period with interrupts disabled within |
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53 | RTEMS is less than |
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54 | RTEMS_MAXIMUM_DISABLE_PERIOD microseconds including the instructions |
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55 | which disable and re-enable interrupts. The time required for |
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56 | the i960CA to generate an interrupt using the sysctl |
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57 | instruction, vectoring to an interrupt handler, and for the |
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58 | RTEMS entry overhead before invoking the user's interrupt |
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59 | handler are a total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK |
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60 | microseconds. These combine to yield |
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61 | a worst case interrupt latency of less than |
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62 | RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK |
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63 | microseconds. [NOTE: The maximum period with interrupts |
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64 | disabled within RTEMS was last calculated for Release |
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65 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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66 | |
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67 | It should be noted again that the maximum period with |
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68 | interrupts disabled within RTEMS is hand-timed. The interrupt |
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69 | vector and entry overhead time was generated on the Cyclone |
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70 | CVME961 benchmark platform using the sysctl instruction as the |
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71 | interrupt source. |
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72 | |
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73 | @section Context Switch |
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74 | |
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75 | The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS |
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76 | microseconds on the Cyclone CVME961 benchmark platform. This |
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77 | time represents the raw context switch time with no user |
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78 | extensions configured. Additional execution time is required |
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79 | when a TSWITCH user extension is configured. The use of the |
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80 | TSWITCH extension is application dependent. Thus, its execution |
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81 | time is not considered part of the base context switch time. |
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82 | |
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83 | The CVME961 has no hardware floating point capability |
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84 | and floating point tasks are not supported. |
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85 | |
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86 | The following table summarizes the context switch |
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87 | times for the CVME961 benchmark platform: |
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88 | |
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