1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @chapter Memory Model |
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10 | |
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11 | @section Introduction |
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12 | |
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13 | A processor may support any combination of memory |
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14 | models ranging from pure physical addressing to complex demand |
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15 | paged virtual memory systems. RTEMS supports a flat memory |
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16 | model which ranges contiguously over the processor's allowable |
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17 | address space. RTEMS does not support segmentation or virtual |
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18 | memory of any kind. The appropriate memory model for RTEMS |
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19 | provided by the targeted processor and related characteristics |
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20 | of that model are described in this chapter. |
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21 | |
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22 | @section Flat Memory Model |
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23 | |
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24 | The i960CA supports a flat 32-bit address space with |
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25 | addresses ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes). |
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26 | Although the i960CA reserves portions of this address space, |
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27 | application code and data may be placed in any non-reserved |
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28 | areas. Each address is represented by a 32-bit value and is |
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29 | byte addressable. The address may be used to reference a single |
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30 | byte, half-word (2-bytes), word (4 bytes), double-word (8 |
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31 | bytes), triple-word (12 bytes) or quad-word (16 bytes). The |
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32 | i960CA does not support virtual memory or segmentation. |
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33 | |
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34 | The i960CA allows the memory space to be partitioned |
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35 | into sixteen regions which may be configured individually as big |
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36 | or little endian. RTEMS assumes that the memory regions in |
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37 | which its code, data, and the RTEMS Workspace reside are |
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38 | configured as little endian. |
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39 | |
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40 | |
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