1 | @ifinfo |
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2 | @node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top |
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3 | @end ifinfo |
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4 | @chapter Interrupt Processing |
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5 | @ifinfo |
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6 | @menu |
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7 | * Interrupt Processing Introduction:: |
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8 | * Interrupt Processing Vectoring of Interrupt Handler:: |
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9 | * Interrupt Processing Interrupt Record:: |
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10 | * Interrupt Processing Interrupt Levels:: |
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11 | * Interrupt Processing Disabling of Interrupts by RTEMS:: |
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12 | * Interrupt Processing Register Cache Flushing:: |
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13 | * Interrupt Processing Interrupt Stack:: |
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14 | @end menu |
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15 | @end ifinfo |
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16 | |
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17 | @ifinfo |
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18 | @node Interrupt Processing Introduction, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing, Interrupt Processing |
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19 | @end ifinfo |
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20 | @section Introduction |
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21 | |
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22 | Different types of processors respond to the |
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23 | occurrence of an interrupt in its own unique fashion. In |
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24 | addition, each processor type provides a control mechanism to |
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25 | allow the proper handling of an interrupt. The processor |
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26 | dependent response to the interrupt which modifies the execution |
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27 | state and results in the modification of the execution stream. |
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28 | This modification usually requires that an interrupt handler |
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29 | utilize the provided control mechanisms to return to the normal |
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30 | processing stream. Although RTEMS hides many of the processor |
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31 | dependent details of interrupt processing, it is important to |
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32 | understand how the RTEMS interrupt manager is mapped onto the |
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33 | processor's unique architecture. Discussed in this chapter are |
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34 | the the processor's response and control mechanisms as they |
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35 | pertain to RTEMS. |
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36 | |
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37 | @ifinfo |
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38 | @node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Record, Interrupt Processing Introduction, Interrupt Processing |
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39 | @end ifinfo |
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40 | @section Vectoring of Interrupt Handler |
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41 | |
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42 | Upon receipt of an interrupt the i960CA |
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43 | automatically performs the following actions: |
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44 | |
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45 | @itemize @bullet |
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46 | @item saves the local register set, |
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47 | |
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48 | @item sets the Frame Pointer (FP) to point to the interrupt |
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49 | stack, |
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50 | |
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51 | @item increments the FP by sixteen (16) to make room for the |
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52 | Interrupt Record, |
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53 | |
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54 | @item saves the current values of the arithmetic-controls (AC) |
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55 | register, the process-controls (PC) register, and the interrupt |
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56 | vector number are saved in the Interrupt Record, |
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57 | |
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58 | @item the CPU sets the Instruction Pointer (IP) to the address |
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59 | of the first instruction in the interrupt handler, |
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60 | |
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61 | @item the return-status field of the Previous Frame Pointer |
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62 | (PFP or R0) register is set to interrupt return, |
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63 | |
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64 | @item sets the PC state bit to interrupted, |
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65 | |
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66 | @item sets the current interrupt disable level in the PC to |
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67 | the level of the current interrupt, and |
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68 | |
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69 | @item disables tracing. |
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70 | @end itemize |
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71 | |
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72 | A nested interrupt is processed similarly by the |
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73 | i960CA with the exception that the Frame Pointer (FP) already |
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74 | points to the interrupt stack. This means that the FP is NOT |
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75 | overwritten before space for the Interrupt Record is allocated. |
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76 | |
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77 | The state flag bit of the saved PC register in the |
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78 | Interrupt Record is examined by RTEMS to determine when an outer |
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79 | most interrupt is being exited. Therefore, the user application |
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80 | code MUST NOT modify this bit. |
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81 | |
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82 | @ifinfo |
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83 | @node Interrupt Processing Interrupt Record, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing |
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84 | @end ifinfo |
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85 | @section Interrupt Record |
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86 | |
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87 | The structure of the Interrupt Record for the i960CA |
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88 | which is placed on the interrupt stack by the processor in |
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89 | response to an interrupt is as follows: |
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90 | |
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91 | @ifset use-ascii |
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92 | @example |
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93 | @group |
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94 | +---------------------------+ |
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95 | | Saved Process Controls | NFP-16 |
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96 | +---------------------------+ |
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97 | | Saved Arithmetic Controls | NFP-12 |
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98 | +---------------------------+ |
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99 | | UNUSED | NFP-8 |
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100 | +---------------------------+ |
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101 | | UNUSED | NFP-4 |
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102 | +---------------------------+ |
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103 | @end group |
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104 | @end example |
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105 | @end ifset |
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106 | |
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107 | @ifset use-tex |
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108 | @sp 1 |
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109 | @tex |
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110 | \centerline{\vbox{\offinterlineskip\halign{ |
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111 | \strut\vrule#& |
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112 | \hbox to 2.00in{\enskip\hfil#\hfil}& |
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113 | \vrule#& |
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114 | \hbox to 1.00in{\enskip\hfil#\hfil} |
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115 | \cr |
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116 | \multispan{3}\hrulefill\cr |
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117 | & Saved Process Controls && NFP-16\cr |
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118 | \multispan{3}\hrulefill\cr |
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119 | & Saved Arithmetic Controls && NFP-12\cr |
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120 | \multispan{3}\hrulefill\cr |
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121 | & UNUSED && NFP-8\cr |
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122 | \multispan{3}\hrulefill\cr |
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123 | & UNUSED && NFP-4\cr |
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124 | \multispan{3}\hrulefill\cr |
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125 | }}\hfil} |
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126 | @end tex |
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127 | @end ifset |
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128 | |
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129 | @ifset use-html |
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130 | @html |
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131 | <CENTER> |
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132 | <TABLE COLS=2 WIDTH="40%" BORDER=2> |
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133 | <TR><TD ALIGN=center><STRONG>Saved Process Controls</STRONG></TD> |
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134 | <TD ALIGN=center>NFP-16</TD></TR> |
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135 | <TR><TD ALIGN=center><STRONG>Saved Arithmetic Controls</STRONG></TD> |
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136 | <TD ALIGN=center>NFP-12</TD></TR> |
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137 | <TR><TD ALIGN=center><STRONG>UNUSED</STRONG></TD> |
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138 | <TD ALIGN=center>NFP-8</TD></TR> |
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139 | <TR><TD ALIGN=center><STRONG>UNUSED</STRONG></TD> |
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140 | <TD ALIGN=center>NFP-4</TD></TR> |
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141 | </TABLE> |
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142 | </CENTER> |
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143 | @end html |
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144 | @end ifset |
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145 | |
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146 | @ifinfo |
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147 | @node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Record, Interrupt Processing |
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148 | @end ifinfo |
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149 | @section Interrupt Levels |
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150 | |
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151 | Thirty-two levels (0-31) of interrupt priorities are |
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152 | supported by the i960CA microprocessor with level thirty-one |
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153 | (31) being the highest priority. Level zero (0) indicates that |
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154 | interrupts are fully enabled. Interrupt requests for interrupts |
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155 | with priorities less than or equal to the current interrupt mask |
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156 | level are ignored. |
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157 | |
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158 | Although RTEMS supports 256 interrupt levels, the |
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159 | i960CA only supports thirty-two. RTEMS interrupt levels 0 |
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160 | through 31 directly correspond to i960CA interrupt levels. All |
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161 | other RTEMS interrupt levels are undefined and their behavior is |
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162 | unpredictable. |
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163 | |
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164 | @ifinfo |
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165 | @node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Register Cache Flushing, Interrupt Processing Interrupt Levels, Interrupt Processing |
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166 | @end ifinfo |
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167 | @section Disabling of Interrupts by RTEMS |
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168 | |
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169 | During the execution of directive calls, critical |
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170 | sections of code may be executed. When these sections are |
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171 | encountered, RTEMS disables interrupts to level thirty-one (31) |
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172 | before the execution of this section and restores them to the |
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173 | previous level upon completion of the section. RTEMS has been |
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174 | optimized to insure that interrupts are disabled for less than |
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175 | RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a |
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176 | RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz i960CA with zero wait states. |
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177 | These numbers will vary based the number of wait states and |
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178 | processor speed present on the target board. [NOTE: This |
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179 | calculation was most recently performed for Release |
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180 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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181 | |
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182 | Non-maskable interrupts (NMI) cannot be disabled, and |
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183 | ISRs which execute at this level MUST NEVER issue RTEMS system |
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184 | calls. If a directive is invoked, unpredictable results may |
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185 | occur due to the inability of RTEMS to protect its critical |
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186 | sections. However, ISRs that make no system calls may safely |
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187 | execute as non-maskable interrupts. |
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188 | |
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189 | @ifinfo |
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190 | @node Interrupt Processing Register Cache Flushing, Interrupt Processing Interrupt Stack, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing |
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191 | @end ifinfo |
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192 | @section Register Cache Flushing |
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193 | |
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194 | The i960CA version of the RTEMS interrupt manager is |
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195 | optimized to insure that the flushreg instruction is only |
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196 | executed when a context switch is necessary. The flushreg |
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197 | instruction flushes the i960CA register set cache and takes (14 |
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198 | + 23 * number of sets flushed) cycles to execute. As the i960CA |
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199 | supports caching of from five to sixteen register sets, this |
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200 | instruction takes from 129 to 382 cycles (3.90 to 11.57 |
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201 | microseconds at 33 Mhz) to execute given no wait state memory. |
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202 | RTEMS flushes the register set cache only at the conclusion of |
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203 | the outermost ISR when a context switch is necessary. The |
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204 | register set cache will not be flushed as part of processing a |
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205 | nested interrupt or when a context switch is not necessary. |
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206 | This optimization is essential to providing high-performance |
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207 | interrupt management on the i960CA. |
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208 | |
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209 | @ifinfo |
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210 | @node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Register Cache Flushing, Interrupt Processing |
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211 | @end ifinfo |
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212 | @section Interrupt Stack |
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213 | |
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214 | On the i960CA, RTEMS allocates the interrupt stack |
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215 | from the Workspace Area. The amount of memory allocated for the |
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216 | interrupt stack is determined by the interrupt_stack_size field |
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217 | in the CPU Configuration Table. During the initialization |
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218 | process, RTEMS will install its interrupt stack. |
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219 | |
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220 | |
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