source: rtems/doc/supplements/i960/callconv.t @ 0609066

4.104.114.84.95
Last change on this file since 0609066 was 4b4d4fde, checked in by Joel Sherrill <joel.sherrill@…>, on 07/31/02 at 00:14:11

2002-07-30 Joel Sherrill <joel@…>

  • callconf.t: Added some markups for fonts and clarified some places.
  • Property mode set to 100644
File size: 3.5 KB
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1@c
2@c  COPYRIGHT (c) 1988-2002.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@chapter Calling Conventions
10
11@section Introduction
12
13Each high-level language compiler generates
14subroutine entry and exit code based upon a set of rules known
15as the compiler's calling convention.   These rules address the
16following issues:
17
18@itemize @bullet
19@item register preservation and usage
20
21@item parameter passing
22
23@item call and return mechanism
24@end itemize
25
26A compiler's calling convention is of importance when
27interfacing to subroutines written in another language either
28assembly or high-level.  Even when the high-level language and
29target processor are the same, different compilers may use
30different calling conventions.  As a result, calling conventions
31are both processor and compiler dependent.
32
33@section Processor Background
34
35All members of the i960 architecture family support
36two methods for performing procedure calls: a RISC-style
37branch-and-link and an integrated call and return mechanism.
38
39On a branch-and-link, the processor branches to the
40invoked procedure and saves the return address in a register,
41@code{G14}.  Typically, the invoked procedure will not invoke another
42procedure and is referred to as a leaf procedure.  Many
43high-level language compilers for the i960 family recognize leaf
44procedures and automatically optimize them to utilize the
45branch-and-link mechanism.  Branch-and-link procedures are
46invoked using the @code{bal} and @code{balx} instructions and return control
47via the @code{bx} instruction.  By convention, @code{G14} is zero when not in
48a leaf procedure.  It is the responsibility of the leaf
49procedure to clear @code{G14} before returning.
50
51The integrated call and return mechanism also
52branches to the invoked procedure and saves the return address
53as did the branch and link mechanism. However, the important
54difference is that the @code{call}, @code{callx}, and @code{calls} instructions save
55the local register set (@code{R0} through @code{R15}) before transferring
56control to the invoked procedure.  The @code{ret} instruction
57automatically restores the previous local register set.  The
58i960CA provides a register cache which can be configured to
59retain the last five to sixteen recent register caches.  When
60the register cache is full, the oldest cached register set is
61written to the stack.
62
63@section Calling Mechanism
64
65All RTEMS directives are invoked using either a @code{call}
66or @code{callx} instruction and return to the user via the @code{ret}
67instruction.
68
69@section Register Usage
70
71As discussed above, the @code{call} and @code{callx} instructions
72automatically save the current contents of the local register
73set (@code{R0} through @code{R15}).  The contents of the local registers will
74be restored as part of returning to the application.  The
75contents of global registers @code{G0} through @code{G7} are not preserved by
76RTEMS directives.
77
78@section Parameter Passing
79
80RTEMS uses the standard i960 family C parameter
81passing mechanism in which @code{G0} contains the first parameter, @code{G1}
82the second,  and so on  for the remaining parameters.  No RTEMS
83directive requires more than six parameters.
84
85@section User-Provided Routines
86
87All user-provided routines invoked by RTEMS, such as
88user extensions, device drivers, and MPCI routines, must also
89adhere to these calling conventions.
90
91@section Leaf Procedures
92
93RTEMS utilizes leaf procedures internally to improve
94performance.  This improves execution speed as well as reducing
95stack usage and the number of register sets which must be cached.
96
97
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