1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @chapter Board Support Packages |
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10 | |
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11 | @section Introduction |
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12 | |
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13 | An RTEMS Board Support Package (BSP) must be designed |
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14 | to support a particular processor and target board combination. |
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15 | This chapter presents a discussion of i960CA specific BSP |
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16 | issues. For more information on developing a BSP, refer to the |
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17 | chapter titled Board Support Packages in the RTEMS |
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18 | Applications User's Guide. |
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19 | |
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20 | @section System Reset |
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21 | |
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22 | An RTEMS based application is initiated when the |
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23 | i960CA processor is reset. When the i960CA is reset, the |
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24 | processor reads an Initial Memory Image (IMI) to establish its |
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25 | state. The IMI consists of the Initialization Boot Record (IBR) |
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26 | and the Process Control Block (PRCB) from an Initial Memory |
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27 | Image (IMI) at location 0xFFFFFF00. The IBR contains the |
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28 | initial bus configuration data, the address of the first |
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29 | instruction to execute after reset, the address of the PRCB, and |
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30 | the checksum used by the processor's self-test. |
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31 | |
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32 | @section Processor Initialization |
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33 | |
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34 | The PRCB contains the base addresses for system data |
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35 | structures, and initial configuration information for the core |
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36 | and integrated peripherals. In particular, the PRCB contains |
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37 | the initial contents of the Arithmetic Control (AC) Register as |
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38 | well as the base addresses of the Interrupt Vector Table, System |
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39 | Procedure Entry Table, Fault Entry Table, and the Control Table. |
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40 | In addition, the PRCB is used to configure the depth of the |
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41 | instruction and register caches and the actions when certain |
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42 | types of faults are encountered. |
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43 | |
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44 | The Process Controls (PC) Register is initialized to |
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45 | 0xC01F2002 which sets the i960CA's interrupt level to 0x1F (31 |
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46 | decimal). In addition, the Interrupt Mask (IMSK) Register |
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47 | (alternately referred to as Special Function Register 1 or sf1) |
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48 | is set to 0x00000000 to mask all external and DMA interrupt |
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49 | sources. Thus, all interrupts are disabled when the first |
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50 | instruction is executed. |
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51 | |
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52 | For more information regarding the i960CA's data |
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53 | structures and their contents, refer to Intel's i960CA User's |
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54 | Manual. |
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