1 | @c |
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2 | @c COPYRIGHT (c) 1988-1998. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @include ../../common/timemac.texi |
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10 | @tex |
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11 | \global\advance \smallskipamount by -4pt |
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12 | @end tex |
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13 | |
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14 | @ifinfo |
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15 | @node CPU386 Timing Data, CPU386 Timing Data Introduction, Timing Specification Terminology, Top |
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16 | @end ifinfo |
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17 | @chapter CPU386 Timing Data |
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18 | @ifinfo |
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19 | @menu |
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20 | * CPU386 Timing Data Introduction:: |
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21 | * CPU386 Timing Data Hardware Platform:: |
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22 | * CPU386 Timing Data Interrupt Latency:: |
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23 | * CPU386 Timing Data Context Switch:: |
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24 | * CPU386 Timing Data Directive Times:: |
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25 | * CPU386 Timing Data Task Manager:: |
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26 | * CPU386 Timing Data Interrupt Manager:: |
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27 | * CPU386 Timing Data Clock Manager:: |
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28 | * CPU386 Timing Data Timer Manager:: |
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29 | * CPU386 Timing Data Semaphore Manager:: |
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30 | * CPU386 Timing Data Message Manager:: |
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31 | * CPU386 Timing Data Event Manager:: |
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32 | * CPU386 Timing Data Signal Manager:: |
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33 | * CPU386 Timing Data Partition Manager:: |
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34 | * CPU386 Timing Data Region Manager:: |
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35 | * CPU386 Timing Data Dual-Ported Memory Manager:: |
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36 | * CPU386 Timing Data I/O Manager:: |
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37 | * CPU386 Timing Data Rate Monotonic Manager:: |
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38 | @end menu |
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39 | @end ifinfo |
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40 | |
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41 | @ifinfo |
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42 | @node CPU386 Timing Data Introduction, CPU386 Timing Data Hardware Platform, CPU386 Timing Data, CPU386 Timing Data |
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43 | @end ifinfo |
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44 | @section Introduction |
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45 | |
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46 | The timing data for the i386 version of RTEMS is |
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47 | provided along with the target dependent aspects concerning the |
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48 | gathering of the timing data. The hardware platform used to |
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49 | gather the times is described to give the reader a better |
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50 | understanding of each directive time provided. Also, provided |
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51 | is a description of the interrupt latency and the context |
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52 | switch times as they pertain to the i386 version of RTEMS. |
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53 | |
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54 | @ifinfo |
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55 | @node CPU386 Timing Data Hardware Platform, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Introduction, CPU386 Timing Data |
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56 | @end ifinfo |
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57 | @section Hardware Platform |
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58 | |
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59 | All times reported except for the maximum period |
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60 | interrupts are disabled by RTEMS were measured using a Force |
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61 | Computers CPU386 board. The CPU386 is a 16 Mhz board with zero |
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62 | wait state dynamic memory and an i80387 numeric coprocessor. |
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63 | One of the count-down timers provided by a Motorola MC68901 was |
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64 | used to measure elapsed time with one microsecond resolution. |
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65 | All sources of hardware interrupts are disabled, although the |
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66 | interrupt level of the i386 allows all interrupts. |
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67 | |
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68 | The maximum period interrupts are disabled was |
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69 | measured by summing the number of CPU cycles required by each |
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70 | assembly language instruction executed while interrupts were |
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71 | disabled. Zero wait state memory was assumed. The total CPU |
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72 | cycles executed with interrupts disabled, including the |
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73 | instructions to disable and enable interrupts, was divided by 16 |
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74 | to simulate a i386 executing at 16 Mhz. |
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75 | |
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76 | @ifinfo |
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77 | @node CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Context Switch, CPU386 Timing Data Hardware Platform, CPU386 Timing Data |
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78 | @end ifinfo |
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79 | @section Interrupt Latency |
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80 | |
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81 | The maximum period with interrupts disabled within |
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82 | RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD microseconds |
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83 | including the instructions |
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84 | which disable and re-enable interrupts. The time required for |
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85 | the i386 to generate an interrupt using the int instruction, |
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86 | vectoring to an interrupt handler, and for the RTEMS entry |
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87 | overhead before invoking the user's interrupt handler are a |
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88 | total of 12 microseconds. These combine to yield a worst case |
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89 | interrupt latency of less |
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90 | RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK |
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91 | microseconds. [NOTE: The |
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92 | maximum period with interrupts disabled within RTEMS was last |
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93 | calculated for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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94 | |
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95 | It should be noted again that the maximum period with |
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96 | interrupts disabled within RTEMS is hand-timed. The interrupt |
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97 | vector and entry overhead time was generated on the Force |
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98 | Computers CPU386 benchmark platform using the int instruction as |
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99 | the interrupt source. |
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100 | |
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101 | @ifinfo |
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102 | @node CPU386 Timing Data Context Switch, CPU386 Timing Data Directive Times, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data |
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103 | @end ifinfo |
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104 | @section Context Switch |
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105 | |
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106 | The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS |
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107 | microseconds on the Force Computers CPU386 benchmark platform. |
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108 | This time represents the raw context switch time with no user |
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109 | extensions configured. Additional execution time is required |
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110 | when a TASK_SWITCH user extension is configured. The use of the |
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111 | TASK_SWITCH extension is application dependent. Thus, its |
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112 | execution time is not considered part of the base context switch |
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113 | time. |
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114 | |
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115 | Since RTEMS was designed specifically for embedded |
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116 | missile applications which are floating point intensive, the |
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117 | executive is optimized to avoid unnecessarily saving and |
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118 | restoring the state of the numeric coprocessor. The state of |
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119 | the numeric coprocessor is only saved when a FLOATING_POINT task |
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120 | is dispatched and that task was not the last task to utilize the |
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121 | coprocessor. In a system with only one FLOATING_POINT task, the |
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122 | state of the numeric coprocessor will never be saved or |
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123 | restored. When the first FLOATING_POINT task is dispatched, |
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124 | RTEMS does not need to save the current state of the numeric |
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125 | coprocessor. |
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126 | |
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127 | The exact amount of time required to save and restore |
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128 | floating point context is dependent on the state of the numeric |
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129 | coprocessor. RTEMS places the coprocessor in the initialized |
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130 | state when a task is started or restarted. Once the task has |
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131 | utilized the coprocessor, it is in the idle state when floating |
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132 | point instructions are not executing and the busy state when |
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133 | floating point instructions are executing. The state of the |
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134 | coprocessor is task specific. |
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135 | |
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136 | The following table summarizes the context switch |
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137 | times for the Force Computers CPU386 benchmark platform: |
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138 | |
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139 | @include timetbl.texi |
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140 | |
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141 | @tex |
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142 | \global\advance \smallskipamount by 4pt |
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143 | @end tex |
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