source: rtems/doc/supplements/i386/intr_NOTIMES.t @ 1e524995

4.104.114.84.95
Last change on this file since 1e524995 was 1e524995, checked in by Joel Sherrill <joel.sherrill@…>, on 02/06/98 at 14:14:30

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1@c
2@c  COPYRIGHT (c) 1988-1998.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@ifinfo
10@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top
11@end ifinfo
12@chapter Interrupt Processing
13@ifinfo
14@menu
15* Interrupt Processing Introduction::
16* Interrupt Processing Vectoring of Interrupt Handler::
17* Interrupt Processing Interrupt Stack Frame::
18* Interrupt Processing Interrupt Levels::
19* Interrupt Processing Disabling of Interrupts by RTEMS::
20* Interrupt Processing Interrupt Stack::
21@end menu
22@end ifinfo
23
24@ifinfo
25@node Interrupt Processing Introduction, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing, Interrupt Processing
26@end ifinfo
27@section Introduction
28
29Different types of processors respond to the
30occurrence of an interrupt in their own unique fashion. In
31addition, each processor type provides a control mechanism to
32allow the proper handling of an interrupt.  The processor
33dependent response to the interrupt modifies the execution state
34and results in the modification of the execution stream. This
35modification usually requires that an interrupt handler utilize
36the provided control mechanisms to return to the normal
37processing stream.  Although RTEMS hides many of the processor
38dependent details of interrupt processing, it is important to
39understand how the RTEMS interrupt manager is mapped onto the
40processor's unique architecture. Discussed in this chapter are
41the the processor's response and control mechanisms as they
42pertain to RTEMS.
43
44@ifinfo
45@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Stack Frame, Interrupt Processing Introduction, Interrupt Processing
46@end ifinfo
47@section Vectoring of Interrupt Handler
48
49Although the i386 supports multiple privilege levels,
50RTEMS and all user software executes at privilege level 0.  This
51decision was made by the RTEMS designers to enhance
52compatibility with processors which do not provide sophisticated
53protection facilities like those of the i386.  This decision
54greatly simplifies the discussion of i386 processing, as one
55need only consider interrupts without privilege transitions.
56
57Upon receipt of an interrupt  the i386 automatically
58performs the following actions:
59
60@itemize @bullet
61@item pushes the EFLAGS register
62
63@item pushes the far address of the interrupted instruction
64
65@item vectors to the interrupt service routine (ISR).
66@end itemize
67
68A nested interrupt is processed similarly by the
69i386.
70
71@ifinfo
72@node Interrupt Processing Interrupt Stack Frame, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
73@end ifinfo
74@section Interrupt Stack Frame
75
76The structure of the Interrupt Stack Frame for the
77i386 which is placed on the interrupt stack by the processor in
78response to an interrupt is as follows:
79
80@ifset use-ascii
81@example
82@group
83               +----------------------+
84               | Old EFLAGS Register  | ESP+8
85               +----------+-----------+
86               |   UNUSED |  Old CS   | ESP+4
87               +----------+-----------+
88               |       Old EIP        | ESP
89               +----------------------+
90@end group
91@end example
92@end ifset
93
94@ifset use-tex
95@sp 1
96@tex
97\centerline{\vbox{\offinterlineskip\halign{
98\strut\vrule#&
99\hbox to 1.00in{\enskip\hfil#\hfil}&
100\vrule#&
101\hbox to 1.00in{\enskip\hfil#\hfil}&
102\vrule#&
103\hbox to 0.75in{\enskip\hfil#\hfil}
104\cr
105\multispan{4}\hrulefill\cr
106& \multispan{3} Old EFLAGS Register\quad&&ESP+8\cr
107\multispan{4}\hrulefill\cr
108&UNUSED &&Old CS &&ESP+4\cr
109\multispan{4}\hrulefill\cr
110& \multispan{3} Old EIP && ESP\cr
111\multispan{4}\hrulefill\cr
112}}\hfil}
113@end tex
114@end ifset
115 
116@ifset use-html
117@html
118<CENTER>
119  <TABLE COLS=3 WIDTH="40%" BORDER=2>
120<TR><TD ALIGN=center COLSPAN=2><STRONG>Old EFLAGS Register</STRONG></TD>
121    <TD ALIGN=center>0x0</TD></TR>
122<TR><TD ALIGN=center><STRONG>UNUSED</STRONG></TD>
123    <TD ALIGN=center><STRONG>Old CS</STRONG></TD>
124    <TD ALIGN=center>0x2</TD></TR>
125<TR><TD ALIGN=center COLSPAN=2><STRONG>Old EIP</STRONG></TD>
126    <TD ALIGN=center>0x4</TD></TR>
127  </TABLE>
128</CENTER>
129@end html
130@end ifset
131
132@ifinfo
133@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack Frame, Interrupt Processing
134@end ifinfo
135@section Interrupt Levels
136
137Although RTEMS supports 256 interrupt levels, the
138i386 only supports two -- enabled and disabled.  Interrupts are
139enabled when the interrupt-enable flag (IF) in the extended
140flags (EFLAGS) is set.  Conversely, interrupt processing is
141inhibited when the IF is cleared.  During a non-maskable
142interrupt, all other interrupts, including other non-maskable
143ones, are inhibited.
144
145RTEMS interrupt levels 0 and 1 such that level zero
146(0) indicates that interrupts are fully enabled and level one
147that interrupts are disabled.  All other RTEMS interrupt levels
148are undefined and their behavior is unpredictable.
149
150@ifinfo
151@node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing
152@end ifinfo
153@section Disabling of Interrupts by RTEMS
154
155During the execution of directive calls, critical
156sections of code may be executed.  When these sections are
157encountered, RTEMS disables interrupts before the execution of
158this section and restores them to the previous level upon
159completion of the section.  RTEMS has been optimized to insure
160that interrupts are disabled for less than RTEMS_MAXIMUM_DISABLE_PERIOD
161microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz i386 with zero
162wait states.  These numbers will vary based the number of wait states
163and processor speed present on the target board.   [NOTE:  The maximum
164period with interrupts disabled within RTEMS was last calculated for
165Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
166
167Non-maskable interrupts (NMI) cannot be disabled, and
168ISRs which execute at this level MUST NEVER issue RTEMS system
169calls.  If a directive is invoked, unpredictable results may
170occur due to the inability of RTEMS to protect its critical
171sections.  However, ISRs that make no system calls may safely
172execute as non-maskable interrupts.
173
174@ifinfo
175@node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing
176@end ifinfo
177@section Interrupt Stack
178
179The i386 family does not support a dedicated hardware
180interrupt stack.  On this processor, RTEMS allocates and manages
181a dedicated interrupt stack.  As part of vectoring a non-nested
182interrupt service routine, RTEMS switches from the stack of the
183interrupted task to a dedicated interrupt stack.  When a
184non-nested interrupt returns, RTEMS switches back to the stack
185of the interrupted stack.  The current stack pointer is not
186altered by RTEMS on nested interrupt.
187
188Without a dedicated interrupt stack, every task in
189the system MUST have enough stack space to accommodate the worst
190case stack usage of that particular task and the interrupt
191service routines COMBINED.  By supporting a dedicated interrupt
192stack, RTEMS significantly lowers the stack requirements for
193each task.
194
195RTEMS allocates the dedicated interrupt stack from
196the Workspace Area.  The amount of memory allocated for the
197interrupt stack is determined by the interrupt_stack_size field
198in the CPU Configuration Table.
199
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