1 | @c |
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2 | @c COPYRIGHT (c) 1988-1998. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top |
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11 | @end ifinfo |
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12 | @chapter Interrupt Processing |
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13 | @ifinfo |
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14 | @menu |
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15 | * Interrupt Processing Introduction:: |
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16 | * Interrupt Processing Vectoring of Interrupt Handler:: |
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17 | * Interrupt Processing Interrupt Stack Frame:: |
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18 | * Interrupt Processing Interrupt Levels:: |
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19 | * Interrupt Processing Disabling of Interrupts by RTEMS:: |
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20 | * Interrupt Processing Interrupt Stack:: |
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21 | @end menu |
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22 | @end ifinfo |
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23 | |
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24 | @ifinfo |
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25 | @node Interrupt Processing Introduction, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing, Interrupt Processing |
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26 | @end ifinfo |
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27 | @section Introduction |
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28 | |
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29 | Different types of processors respond to the |
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30 | occurrence of an interrupt in their own unique fashion. In |
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31 | addition, each processor type provides a control mechanism to |
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32 | allow the proper handling of an interrupt. The processor |
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33 | dependent response to the interrupt modifies the execution state |
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34 | and results in the modification of the execution stream. This |
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35 | modification usually requires that an interrupt handler utilize |
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36 | the provided control mechanisms to return to the normal |
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37 | processing stream. Although RTEMS hides many of the processor |
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38 | dependent details of interrupt processing, it is important to |
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39 | understand how the RTEMS interrupt manager is mapped onto the |
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40 | processor's unique architecture. Discussed in this chapter are |
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41 | the the processor's response and control mechanisms as they |
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42 | pertain to RTEMS. |
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43 | |
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44 | @ifinfo |
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45 | @node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Stack Frame, Interrupt Processing Introduction, Interrupt Processing |
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46 | @end ifinfo |
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47 | @section Vectoring of Interrupt Handler |
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48 | |
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49 | Although the i386 supports multiple privilege levels, |
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50 | RTEMS and all user software executes at privilege level 0. This |
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51 | decision was made by the RTEMS designers to enhance |
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52 | compatibility with processors which do not provide sophisticated |
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53 | protection facilities like those of the i386. This decision |
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54 | greatly simplifies the discussion of i386 processing, as one |
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55 | need only consider interrupts without privilege transitions. |
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56 | |
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57 | Upon receipt of an interrupt the i386 automatically |
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58 | performs the following actions: |
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59 | |
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60 | @itemize @bullet |
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61 | @item pushes the EFLAGS register |
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62 | |
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63 | @item pushes the far address of the interrupted instruction |
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64 | |
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65 | @item vectors to the interrupt service routine (ISR). |
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66 | @end itemize |
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67 | |
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68 | A nested interrupt is processed similarly by the |
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69 | i386. |
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70 | |
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71 | @ifinfo |
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72 | @node Interrupt Processing Interrupt Stack Frame, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing |
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73 | @end ifinfo |
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74 | @section Interrupt Stack Frame |
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75 | |
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76 | The structure of the Interrupt Stack Frame for the |
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77 | i386 which is placed on the interrupt stack by the processor in |
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78 | response to an interrupt is as follows: |
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79 | |
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80 | @ifset use-ascii |
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81 | @example |
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82 | @group |
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83 | +----------------------+ |
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84 | | Old EFLAGS Register | ESP+8 |
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85 | +----------+-----------+ |
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86 | | UNUSED | Old CS | ESP+4 |
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87 | +----------+-----------+ |
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88 | | Old EIP | ESP |
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89 | +----------------------+ |
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90 | @end group |
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91 | @end example |
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92 | @end ifset |
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93 | |
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94 | @ifset use-tex |
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95 | @sp 1 |
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96 | @tex |
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97 | \centerline{\vbox{\offinterlineskip\halign{ |
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98 | \strut\vrule#& |
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99 | \hbox to 1.00in{\enskip\hfil#\hfil}& |
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100 | \vrule#& |
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101 | \hbox to 1.00in{\enskip\hfil#\hfil}& |
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102 | \vrule#& |
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103 | \hbox to 0.75in{\enskip\hfil#\hfil} |
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104 | \cr |
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105 | \multispan{4}\hrulefill\cr |
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106 | & \multispan{3} Old EFLAGS Register\quad&&ESP+8\cr |
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107 | \multispan{4}\hrulefill\cr |
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108 | &UNUSED &&Old CS &&ESP+4\cr |
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109 | \multispan{4}\hrulefill\cr |
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110 | & \multispan{3} Old EIP && ESP\cr |
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111 | \multispan{4}\hrulefill\cr |
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112 | }}\hfil} |
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113 | @end tex |
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114 | @end ifset |
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115 | |
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116 | @ifset use-html |
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117 | @html |
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118 | <CENTER> |
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119 | <TABLE COLS=3 WIDTH="40%" BORDER=2> |
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120 | <TR><TD ALIGN=center COLSPAN=2><STRONG>Old EFLAGS Register</STRONG></TD> |
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121 | <TD ALIGN=center>0x0</TD></TR> |
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122 | <TR><TD ALIGN=center><STRONG>UNUSED</STRONG></TD> |
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123 | <TD ALIGN=center><STRONG>Old CS</STRONG></TD> |
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124 | <TD ALIGN=center>0x2</TD></TR> |
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125 | <TR><TD ALIGN=center COLSPAN=2><STRONG>Old EIP</STRONG></TD> |
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126 | <TD ALIGN=center>0x4</TD></TR> |
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127 | </TABLE> |
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128 | </CENTER> |
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129 | @end html |
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130 | @end ifset |
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131 | |
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132 | @ifinfo |
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133 | @node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack Frame, Interrupt Processing |
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134 | @end ifinfo |
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135 | @section Interrupt Levels |
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136 | |
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137 | Although RTEMS supports 256 interrupt levels, the |
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138 | i386 only supports two -- enabled and disabled. Interrupts are |
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139 | enabled when the interrupt-enable flag (IF) in the extended |
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140 | flags (EFLAGS) is set. Conversely, interrupt processing is |
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141 | inhibited when the IF is cleared. During a non-maskable |
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142 | interrupt, all other interrupts, including other non-maskable |
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143 | ones, are inhibited. |
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144 | |
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145 | RTEMS interrupt levels 0 and 1 such that level zero |
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146 | (0) indicates that interrupts are fully enabled and level one |
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147 | that interrupts are disabled. All other RTEMS interrupt levels |
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148 | are undefined and their behavior is unpredictable. |
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149 | |
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150 | @ifinfo |
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151 | @node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing |
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152 | @end ifinfo |
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153 | @section Disabling of Interrupts by RTEMS |
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154 | |
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155 | During the execution of directive calls, critical |
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156 | sections of code may be executed. When these sections are |
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157 | encountered, RTEMS disables interrupts before the execution of |
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158 | this section and restores them to the previous level upon |
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159 | completion of the section. RTEMS has been optimized to insure |
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160 | that interrupts are disabled for less than RTEMS_MAXIMUM_DISABLE_PERIOD |
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161 | microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz i386 with zero |
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162 | wait states. These numbers will vary based the number of wait states |
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163 | and processor speed present on the target board. [NOTE: The maximum |
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164 | period with interrupts disabled within RTEMS was last calculated for |
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165 | Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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166 | |
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167 | Non-maskable interrupts (NMI) cannot be disabled, and |
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168 | ISRs which execute at this level MUST NEVER issue RTEMS system |
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169 | calls. If a directive is invoked, unpredictable results may |
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170 | occur due to the inability of RTEMS to protect its critical |
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171 | sections. However, ISRs that make no system calls may safely |
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172 | execute as non-maskable interrupts. |
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173 | |
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174 | @ifinfo |
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175 | @node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing |
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176 | @end ifinfo |
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177 | @section Interrupt Stack |
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178 | |
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179 | The i386 family does not support a dedicated hardware |
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180 | interrupt stack. On this processor, RTEMS allocates and manages |
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181 | a dedicated interrupt stack. As part of vectoring a non-nested |
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182 | interrupt service routine, RTEMS switches from the stack of the |
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183 | interrupted task to a dedicated interrupt stack. When a |
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184 | non-nested interrupt returns, RTEMS switches back to the stack |
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185 | of the interrupted stack. The current stack pointer is not |
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186 | altered by RTEMS on nested interrupt. |
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187 | |
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188 | Without a dedicated interrupt stack, every task in |
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189 | the system MUST have enough stack space to accommodate the worst |
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190 | case stack usage of that particular task and the interrupt |
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191 | service routines COMBINED. By supporting a dedicated interrupt |
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192 | stack, RTEMS significantly lowers the stack requirements for |
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193 | each task. |
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194 | |
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195 | RTEMS allocates the dedicated interrupt stack from |
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196 | the Workspace Area. The amount of memory allocated for the |
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197 | interrupt stack is determined by the interrupt_stack_size field |
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198 | in the CPU Configuration Table. |
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199 | |
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