1 | @c |
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2 | @c COPYRIGHT (c) 1988-1998. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top |
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11 | @end ifinfo |
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12 | @chapter Board Support Packages |
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13 | @ifinfo |
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14 | @menu |
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15 | * Board Support Packages Introduction:: |
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16 | * Board Support Packages System Reset:: |
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17 | * Board Support Packages Processor Initialization:: |
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18 | @end menu |
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19 | @end ifinfo |
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20 | |
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21 | @ifinfo |
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22 | @node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages |
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23 | @end ifinfo |
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24 | @section Introduction |
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25 | |
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26 | An RTEMS Board Support Package (BSP) must be designed to support a |
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27 | particular processor and target board combination. This chapter presents a |
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28 | discussion of i386 specific BSP issues. For more information on developing |
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29 | a BSP, refer to the chapter titled Board Support Packages in the RTEMS |
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30 | Applications User's Guide. |
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31 | |
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32 | @ifinfo |
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33 | @node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages |
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34 | @end ifinfo |
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35 | @section System Reset |
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36 | |
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37 | An RTEMS based application is initiated when the i386 |
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38 | processor is reset. When the i386 is reset, |
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39 | |
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40 | @itemize @bullet |
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41 | |
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42 | @item The EAX register is set to indicate the results of the processor's |
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43 | power-up self test. If the self-test was not executed, the contents of |
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44 | this register are undefined. Otherwise, a non-zero value indicates the |
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45 | processor is faulty and a zero value indicates a successful self-test. |
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46 | |
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47 | @item The DX register holds a component identifier and revision level. DH |
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48 | contains 3 to indicate an i386 component and DL contains a unique revision |
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49 | level indicator. |
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50 | |
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51 | @item Control register zero (CR0) is set such that the processor is in real |
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52 | mode with paging disabled. Other portions of CR0 are used to indicate the |
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53 | presence of a numeric coprocessor. |
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54 | |
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55 | @item All bits in the extended flags register (EFLAG) which are not |
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56 | permanently set are cleared. This inhibits all maskable interrupts. |
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57 | |
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58 | @item The Interrupt Descriptor Register (IDTR) is set to point at address |
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59 | zero. |
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60 | |
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61 | @item All segment registers are set to zero. |
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62 | |
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63 | @item The instruction pointer is set to 0x0000FFF0. The first instruction |
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64 | executed after a reset is actually at 0xFFFFFFF0 because the i386 asserts |
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65 | the upper twelve address until the first intersegment (FAR) JMP or CALL |
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66 | instruction. When a JMP or CALL is executed, the upper twelve address |
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67 | lines are lowered and the processor begins executing in the first megabyte |
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68 | of memory. |
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69 | |
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70 | @end itemize |
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71 | |
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72 | Typically, an intersegment JMP to the application's initialization code is |
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73 | placed at address 0xFFFFFFF0. |
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74 | |
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75 | @ifinfo |
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76 | @node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages |
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77 | @end ifinfo |
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78 | @section Processor Initialization |
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79 | |
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80 | This initialization code is responsible for initializing all data |
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81 | structures required by the i386 in protected mode and for actually entering |
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82 | protected mode. The i386 must be placed in protected mode and the segment |
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83 | registers and associated selectors must be initialized before the |
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84 | initialize_executive directive is invoked. |
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85 | |
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86 | The initialization code is responsible for initializing the Global |
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87 | Descriptor Table such that the i386 is in the thirty-two bit flat memory |
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88 | model with paging disabled. In this mode, the i386 automatically converts |
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89 | every address from a logical to a physical address each time it is used. |
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90 | For more information on the memory model used by RTEMS, please refer to the |
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91 | Memory Model chapter in this document. |
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92 | |
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93 | Since the processor is in real mode upon reset, the processor must be |
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94 | switched to protected mode before RTEMS can execute. Before switching to |
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95 | protected mode, at least one descriptor table and two descriptors must be |
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96 | created. Descriptors are needed for a code segment and a data segment. ( |
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97 | This will give you the flat memory model.) The stack can be placed in a |
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98 | normal read/write data segment, so no descriptor for the stack is needed. |
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99 | Before the GDT can be used, the base address and limit must be loaded into |
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100 | the GDTR register using an LGDT instruction. |
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101 | |
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102 | If the hardware allows an NMI to be generated, you need to create the IDT |
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103 | and a gate for the NMI interrupt handler. Before the IDT can be used, the |
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104 | base address and limit for the idt must be loaded into the IDTR register |
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105 | using an LIDT instruction. |
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106 | |
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107 | Protected mode is entered by setting thye PE bit in the CR0 register. |
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108 | Either a LMSW or MOV CR0 instruction may be used to set this bit. Because |
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109 | the processor overlaps the interpretation of several instructions, it is |
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110 | necessary to discard the instructions from the read-ahead cache. A JMP |
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111 | instruction immediately after the LMSW changes the flow and empties the |
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112 | processor if intructions which have been pre-fetched and/or decoded. At |
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113 | this point, the processor is in protected mode and begins to perform |
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114 | protected mode application initialization. |
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115 | |
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116 | If the application requires that the IDTR be some value besides zero, then |
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117 | it should set it to the required value at this point. All tasks share the |
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118 | same i386 IDTR value. Because interrupts are enabled automatically by |
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119 | RTEMS as part of the initialize_executive directive, the IDTR MUST be set |
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120 | properly before this directive is invoked to insure correct interrupt |
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121 | vectoring. If processor caching is to be utilized, then it should be |
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122 | enabled during the reset application initialization code. The reset code |
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123 | which is executed before the call to initialize_executive has the following |
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124 | requirements: |
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125 | |
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126 | For more information regarding the i386s data structures and their |
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127 | contents, refer to Intel's 386 Programmer's Reference Manual. |
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128 | |
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