1 | @c |
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2 | @c COPYRIGHT (c) 1988-1998. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top |
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11 | @end ifinfo |
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12 | @chapter Board Support Packages |
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13 | @ifinfo |
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14 | @menu |
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15 | * Board Support Packages Introduction:: |
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16 | * Board Support Packages System Reset:: |
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17 | * Board Support Packages Processor Initialization:: |
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18 | @end menu |
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19 | @end ifinfo |
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20 | |
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21 | @ifinfo |
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22 | @node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages |
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23 | @end ifinfo |
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24 | @section Introduction |
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25 | |
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26 | An RTEMS Board Support Package (BSP) must be designed |
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27 | to support a particular processor and target board combination. |
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28 | This chapter presents a discussion of i386 specific BSP issues. |
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29 | For more information on developing a BSP, refer to the chapter |
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30 | titled Board Support Packages in the RTEMS |
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31 | Applications User's Guide. |
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32 | |
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33 | @ifinfo |
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34 | @node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages |
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35 | @end ifinfo |
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36 | @section System Reset |
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37 | |
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38 | An RTEMS based application is initiated when the i386 |
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39 | processor is reset. When the i386 is reset, |
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40 | |
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41 | @itemize @bullet |
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42 | @item The EAX register is set to indicate the results of the |
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43 | processor's power-up self test. If the self-test was not |
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44 | executed, the contents of this register are undefined. |
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45 | Otherwise, a non-zero value indicates the processor is faulty |
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46 | and a zero value indicates a successful self-test. |
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47 | |
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48 | @item The DX register holds a component identifier and |
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49 | revision level. DH contains 3 to indicate an i386 component and |
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50 | DL contains a unique revision level indicator. |
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51 | |
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52 | @item Control register zero (CR0) is set such that the |
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53 | processor is in real mode with paging disabled. Other portions |
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54 | of CR0 are used to indicate the presence of a numeric |
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55 | coprocessor. |
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56 | |
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57 | @item All bits in the extended flags register (EFLAG) which |
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58 | are not permanently set are cleared. This inhibits all maskable |
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59 | interrupts. |
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60 | |
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61 | @item The Interrupt Descriptor Register (IDTR) is set to point |
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62 | at address zero. |
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63 | |
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64 | @item All segment registers are set to zero. |
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65 | |
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66 | @item The instruction pointer is set to 0x0000FFF0. The |
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67 | first instruction executed after a reset is actually at |
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68 | 0xFFFFFFF0 because the i386 asserts the upper twelve address |
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69 | until the first intersegment (FAR) JMP or CALL instruction. |
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70 | When a JMP or CALL is executed, the upper twelve address lines |
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71 | are lowered and the processor begins executing in the first |
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72 | megabyte of memory. |
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73 | @end itemize |
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74 | |
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75 | Typically, an intersegment JMP to the application's |
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76 | initialization code is placed at address 0xFFFFFFF0. |
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77 | |
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78 | @ifinfo |
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79 | @node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages |
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80 | @end ifinfo |
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81 | @section Processor Initialization |
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82 | |
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83 | This initialization code is responsible for |
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84 | initializing all data structures required by the i386 in |
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85 | protected mode and for actually entering protected mode. The |
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86 | i386 must be placed in protected mode and the segment registers |
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87 | and associated selectors must be initialized before the |
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88 | initialize_executive directive is invoked. |
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89 | |
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90 | The initialization code is responsible for |
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91 | initializing the Global Descriptor Table such that the i386 is |
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92 | in the thirty-two bit flat memory model with paging disabled. |
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93 | In this mode, the i386 automatically converts every address from |
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94 | a logical to a physical address each time it is used. For more |
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95 | information on the memory model used by RTEMS, please refer to |
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96 | the Memory Model chapter in this document. |
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97 | |
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98 | If the application requires that the IDTR be some |
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99 | value besides zero, then it should set it to the required value |
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100 | at this point. All tasks share the same i386 IDTR value. |
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101 | Because interrupts are enabled automatically by RTEMS as part of |
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102 | the initialize_executive directive, the IDTR MUST be set |
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103 | properly before this directive is invoked to insure correct |
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104 | interrupt vectoring. If processor caching is to be utilized, |
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105 | then it should be enabled during the reset application |
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106 | initialization code. The reset code which is executed before |
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107 | the call to initialize_executive has the following requirements: |
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108 | |
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109 | For more information regarding the i386s data |
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110 | structures and their contents, refer to Intel's 386 |
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111 | Programmer's Reference Manual. |
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112 | |
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