1 | @c |
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2 | @c COPYRIGHT (c) 1988-1997. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top |
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11 | @end ifinfo |
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12 | @chapter Interrupt Processing |
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13 | @ifinfo |
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14 | @menu |
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15 | * Interrupt Processing Introduction:: |
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16 | * Interrupt Processing Vectoring of Interrupt Handler:: |
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17 | * Interrupt Processing Interrupt Stack Frame:: |
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18 | * Interrupt Processing External Interrupts and Traps:: |
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19 | * Interrupt Processing Interrupt Levels:: |
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20 | * Interrupt Processing Disabling of Interrupts by RTEMS:: |
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21 | @end menu |
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22 | @end ifinfo |
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23 | |
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24 | @ifinfo |
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25 | @node Interrupt Processing Introduction, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing, Interrupt Processing |
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26 | @end ifinfo |
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27 | @section Introduction |
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28 | |
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29 | Different types of processors respond to the |
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30 | occurence of an interrupt in their own unique fashion. In |
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31 | addition, each processor type provides a control mechanism to |
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32 | allow for the proper handling of an interrupt. The processor |
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33 | dependent response to the interrupt modifies the current |
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34 | execution state and results in a change in the execution stream. |
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35 | Most processors require that an interrupt handler utilize some |
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36 | special control mechanisms to return to the normal processing |
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37 | stream. Although RTEMS hides many of the processor dependent |
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38 | details of interrupt processing, it is important to understand |
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39 | how the RTEMS interrupt manager is mapped onto the processor's |
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40 | unique architecture. Discussed in this chapter are the PA-RISC's |
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41 | interrupt response and control mechanisms as they pertain to |
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42 | RTEMS. |
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43 | |
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44 | @ifinfo |
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45 | @node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Stack Frame, Interrupt Processing Introduction, Interrupt Processing |
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46 | @end ifinfo |
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47 | @section Vectoring of Interrupt Handler |
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48 | |
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49 | Upon receipt of an interrupt the PA-RISC |
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50 | automatically performs the following actions: |
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51 | |
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52 | @itemize @bullet |
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53 | @item The PSW (Program Status Word) is saved in the IPSW |
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54 | (Interrupt Program Status Word). |
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55 | |
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56 | @item The current privilege level is set to 0. |
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57 | |
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58 | @item The following defined bits in the PSW are set: |
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59 | |
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60 | @item E bit is set to the default endian bit |
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61 | |
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62 | @item M bit is set to 1 if the interrupt is a high-priority |
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63 | machine check and 0 otherwise |
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64 | |
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65 | @item Q bit is set to zero thuse freezing the IIA |
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66 | (Instruction Address) queues |
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67 | |
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68 | @item C and D bits are set to zero thus disabling all |
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69 | protection and translation. |
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70 | |
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71 | @item I bit is set to zero this disabling all external, |
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72 | powerfail, and low-priority machine check interrupts. |
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73 | |
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74 | @item All others bits are set to zero. |
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75 | |
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76 | @item General purpose registers r1, r8, r9, r16, r17, r24, and |
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77 | r25 are copied to the shadow registers. |
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78 | |
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79 | @item Execution begins at the address given by the formula: |
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80 | Interruption Vector Address + (32 * interrupt vector number). |
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81 | @end itemize |
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82 | |
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83 | Once the processor has completed the actions it is is |
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84 | required to perform for each interrupt, the RTEMS interrupt |
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85 | management code (the beginning of which is stored in the |
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86 | Interruption Vector Table) gains control and performs the |
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87 | following actions upon each interrupt: |
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88 | |
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89 | @itemize @bullet |
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90 | @item returns the processor to "virtual mode" thus reenabling |
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91 | all code and data address translation. |
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92 | |
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93 | @item saves all necessary interrupt state information |
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94 | |
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95 | @item saves all floating point registers |
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96 | |
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97 | @item saves all integer registers |
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98 | |
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99 | @item switches the current stack to the interrupt stack |
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100 | |
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101 | @item dispatches to the appropriate user provided interrupt |
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102 | service routine (ISR). If the ISR was installed with the |
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103 | interrupt_catch directive, then it will be executed at this. |
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104 | Because, the RTEMS interrupt handler saves all registers which |
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105 | are not preserved according to the calling conventions and |
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106 | invokes the application's ISR, the ISR can easily be written in |
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107 | a high-level language. |
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108 | @end itemize |
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109 | |
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110 | RTEMS refers to the combination of the interrupt |
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111 | state information and registers saved when vectoring an |
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112 | interrupt as the Interrupt Stack Frame (ISF). A nested |
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113 | interrupt is processed similarly by the PA-RISC and RTEMS with |
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114 | the exception that the nested interrupt occurred while executing |
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115 | on the interrupt stack and, thus, the current stack need not be |
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116 | switched. |
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117 | |
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118 | @ifinfo |
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119 | @node Interrupt Processing Interrupt Stack Frame, Interrupt Processing External Interrupts and Traps, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing |
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120 | @end ifinfo |
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121 | @section Interrupt Stack Frame |
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122 | |
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123 | The PA-RISC architecture does not alter the stack |
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124 | while processing interrupts. However, RTEMS does save |
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125 | information on the stack as part of processing an interrupt. |
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126 | This following shows the format of the Interrupt Stack Frame for |
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127 | the PA-RISC as defined by RTEMS: |
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128 | |
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129 | @example |
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130 | @group |
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131 | +------------------------+ |
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132 | | Interrupt Context | 0xXXX |
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133 | +------------------------+ |
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134 | | Integer Context | 0xXXX |
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135 | +------------------------+ |
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136 | | Floating Point Context | 0xXXX |
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137 | +------------------------+ |
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138 | @end group |
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139 | @end example |
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140 | |
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141 | @ifinfo |
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142 | @node Interrupt Processing External Interrupts and Traps, Interrupt Processing Interrupt Levels, Interrupt Processing Interrupt Stack Frame, Interrupt Processing |
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143 | @end ifinfo |
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144 | @section External Interrupts and Traps |
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145 | |
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146 | In addition to the thirty-two unique interrupt |
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147 | sources supported by the PA-RISC architecture, RTEMS also |
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148 | supports the installation of handlers for each of the thirty-two |
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149 | external interrupts supported by the PA-RISC architecture. |
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150 | Except for interrupt vector 4, each of the interrupt vectors 0 |
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151 | through 31 may be associated with a user-provided interrupt |
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152 | handler. Interrupt vector 4 is used for external interrupts. |
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153 | When an external interrupt occurs, the RTEMS external interrupt |
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154 | handler is invoked and the actual interrupt source is indicated |
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155 | by status bits in the EIR (External Interrupt Request) register. |
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156 | The RTEMS external interrupt handler (or interrupt vector four) |
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157 | examines the EIR to determine which interrupt source requires |
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158 | servicing. |
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159 | |
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160 | RTEMS supports sixty-four interrupt vectors for the |
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161 | PA-RISC. Vectors 0 through 31 map to the normal interrupt |
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162 | sources while RTEMS interrupt vectors 32 through 63 are directly |
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163 | associated with the external interrupt sources indicated by bits |
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164 | 0 through 31 in the EIR. |
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165 | |
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166 | The exact set of interrupt sources which are checked |
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167 | for by the RTEMS external interrupt handler and the order in |
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168 | which they are checked are configured by the user in the CPU |
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169 | Configuration Table. If an external interrupt occurs which does |
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170 | not have a handler configured, then the spurious interrupt |
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171 | handler will be invoked. The spurious interrupt handler may |
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172 | also be specifiec by the user in the CPU Configuration Table. |
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173 | |
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174 | @ifinfo |
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175 | @node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing External Interrupts and Traps, Interrupt Processing |
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176 | @end ifinfo |
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177 | @section Interrupt Levels |
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178 | |
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179 | Two levels (enabled and disabled) of interrupt |
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180 | priorities are supported by the PA-RISC architecture. Level |
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181 | zero (0) indicates that interrupts are fully enabled (i.e. the I |
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182 | bit of the PSW is 1). Level one (1) indicates that interrupts |
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183 | are disabled (i.e. the I bit of the PSW is 0). Thirty-two |
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184 | independent sources of external interrupts are supported by the |
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185 | PA-RISC architecture. Each of these interrupts sources may be |
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186 | individually enabled or disabled. When processor interrupts are |
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187 | disabled, all sources of external interrupts are ignored. When |
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188 | processor interrupts are enabled, the EIR (External Interrupt |
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189 | Request) register is used to determine which sources are |
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190 | currently allowed to generate interrupts. |
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191 | |
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192 | Although RTEMS supports 256 interrupt levels, the |
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193 | PA-RISC architecture only supports two. RTEMS interrupt level 0 |
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194 | indicates that interrupts are enabled and level 1 indicates that |
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195 | interrupts are disabled. All other RTEMS interrupt levels are |
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196 | undefined and their behavior is unpredictable. |
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197 | |
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198 | @ifinfo |
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199 | @node Interrupt Processing Disabling of Interrupts by RTEMS, Default Fatal Error Processing, Interrupt Processing Interrupt Levels, Interrupt Processing |
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200 | @end ifinfo |
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201 | @section Disabling of Interrupts by RTEMS |
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202 | |
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203 | During the execution of directive calls, critical |
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204 | sections of code may be executed. When these sections are |
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205 | encountered, RTEMS disables external interrupts by setting the I |
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206 | bit in the PSW to 0 before the execution of this section and |
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207 | restores them to the previous level upon completion of the |
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208 | section. RTEMS has been optimized to insure that interrupts are |
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209 | disabled for less than XXX instructions when compiled with GNU |
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210 | CC at optimization level 4. The exact execution time will vary |
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211 | based on the based on the processor implementation, amount of |
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212 | cache, the number of wait states for primary memory, and |
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213 | processor speed present on the target board. |
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214 | |
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215 | Non-maskable interrupts (NMI) such as high-priority |
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216 | machine checks cannot be disabled, and ISRs which execute at |
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217 | this level MUST NEVER issue RTEMS system calls. If a directive |
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218 | is invoked, unpredictable results may occur due to the inability |
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219 | of RTEMS to protect its critical sections. However, ISRs that |
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220 | make no system calls may safely execute as non-maskable |
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221 | interrupts. |
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222 | |
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