source: rtems/doc/supplements/hppa1_1/intr_NOTIMES.t @ 139b2e4a

4.104.114.84.95
Last change on this file since 139b2e4a was 139b2e4a, checked in by Joel Sherrill <joel.sherrill@…>, on 06/04/97 at 18:32:07

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1@c
2@c  COPYRIGHT (c) 1988-1997.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@ifinfo
10@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top
11@end ifinfo
12@chapter Interrupt Processing
13@ifinfo
14@menu
15* Interrupt Processing Introduction::
16* Interrupt Processing Vectoring of Interrupt Handler::
17* Interrupt Processing Interrupt Stack Frame::
18* Interrupt Processing External Interrupts and Traps::
19* Interrupt Processing Interrupt Levels::
20* Interrupt Processing Disabling of Interrupts by RTEMS::
21@end menu
22@end ifinfo
23
24@ifinfo
25@node Interrupt Processing Introduction, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing, Interrupt Processing
26@end ifinfo
27@section Introduction
28
29Different types of processors respond to the
30occurence of an interrupt in their own unique fashion. In
31addition, each processor type provides a control mechanism to
32allow for the proper handling of an interrupt.  The processor
33dependent response to the interrupt modifies the current
34execution state and results in a change in the execution stream.
35Most processors require that an interrupt handler utilize some
36special control mechanisms to return to the normal processing
37stream.  Although RTEMS hides many of the processor dependent
38details of interrupt processing, it is important to understand
39how the RTEMS interrupt manager is mapped onto the processor's
40unique architecture. Discussed in this chapter are the PA-RISC's
41interrupt response and control mechanisms as they pertain to
42RTEMS.
43
44@ifinfo
45@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Stack Frame, Interrupt Processing Introduction, Interrupt Processing
46@end ifinfo
47@section Vectoring of Interrupt Handler
48
49Upon receipt of an interrupt the PA-RISC
50automatically performs the following actions:
51
52@itemize @bullet
53@item The PSW (Program Status Word) is saved in the IPSW
54(Interrupt Program Status Word).
55
56@item The current privilege level is set to 0.
57
58@item The following defined bits in the PSW are set:
59
60@item E bit is set to the default endian bit
61
62@item M bit is set to 1 if the interrupt is a high-priority
63machine check and 0 otherwise
64
65@item Q bit is set to zero thuse freezing the IIA
66(Instruction Address) queues
67
68@item C and D bits are set to zero thus disabling all
69protection and translation.
70
71@item I bit is set to zero this disabling all external,
72powerfail, and low-priority machine check interrupts.
73
74@item All others bits are set to zero.
75
76@item General purpose registers r1, r8, r9, r16, r17, r24, and
77r25 are copied to the shadow registers.
78
79@item Execution begins at the address given by the formula:
80Interruption Vector Address + (32 * interrupt vector number).
81@end itemize
82
83Once the processor has completed the actions it is is
84required to perform for each interrupt, the  RTEMS interrupt
85management code (the beginning of which is stored in the
86Interruption Vector Table) gains control and performs the
87following actions upon each interrupt:
88
89@itemize @bullet
90@item returns the processor to "virtual mode" thus reenabling
91all code and data address translation.
92
93@item saves all necessary interrupt state information
94
95@item saves all floating point registers
96
97@item saves all integer registers
98
99@item switches the current stack to the interrupt stack
100
101@item dispatches to the appropriate user provided interrupt
102service routine (ISR).  If the ISR was installed with the
103interrupt_catch directive, then it will be executed at this.
104Because, the RTEMS interrupt handler saves all registers which
105are not preserved according to the calling conventions and
106invokes the application's ISR, the ISR can easily be written in
107a high-level language.
108@end itemize
109
110RTEMS refers to the combination of the interrupt
111state information and registers saved when vectoring an
112interrupt as the Interrupt Stack Frame (ISF).  A nested
113interrupt is processed similarly by the PA-RISC and RTEMS with
114the exception that the nested interrupt occurred while executing
115on the interrupt stack and, thus, the current stack need not be
116switched.
117
118@ifinfo
119@node Interrupt Processing Interrupt Stack Frame, Interrupt Processing External Interrupts and Traps, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
120@end ifinfo
121@section Interrupt Stack Frame
122
123The PA-RISC architecture does not alter the stack
124while processing interrupts.  However, RTEMS does save
125information on the stack as part of processing an interrupt.
126This following shows the format of the Interrupt Stack Frame for
127the PA-RISC as defined by RTEMS:
128
129@example
130@group
131               +------------------------+
132               |    Interrupt Context   | 0xXXX
133               +------------------------+
134               |     Integer Context    | 0xXXX
135               +------------------------+
136               | Floating Point Context | 0xXXX
137               +------------------------+
138@end group
139@end example
140
141@ifinfo
142@node Interrupt Processing External Interrupts and Traps, Interrupt Processing Interrupt Levels, Interrupt Processing Interrupt Stack Frame, Interrupt Processing
143@end ifinfo
144@section External Interrupts and Traps
145
146In addition to the thirty-two unique interrupt
147sources supported by the PA-RISC architecture, RTEMS also
148supports the installation of handlers for each of the thirty-two
149external interrupts supported by the PA-RISC architecture.
150Except for interrupt vector 4, each of the interrupt vectors 0
151through 31 may be associated with a user-provided interrupt
152handler.  Interrupt vector 4 is used for external interrupts.
153When an external interrupt occurs, the RTEMS external interrupt
154handler is invoked and the actual interrupt source is indicated
155by status bits in the EIR (External Interrupt Request) register.
156The RTEMS external interrupt handler (or interrupt vector four)
157examines the EIR to determine which interrupt source requires
158servicing.
159
160RTEMS supports sixty-four interrupt vectors for the
161PA-RISC.  Vectors 0 through 31 map to the normal interrupt
162sources while RTEMS interrupt vectors 32 through 63 are directly
163associated with the external interrupt sources indicated by bits
1640 through 31 in the EIR.
165
166The exact set of interrupt sources which are checked
167for by the RTEMS external interrupt handler and the order in
168which they are checked are configured by the user in the CPU
169Configuration Table.  If an external interrupt occurs which does
170not have a handler configured, then the spurious interrupt
171handler will be invoked.  The spurious interrupt handler may
172also be specifiec by the user in the CPU Configuration Table.
173
174@ifinfo
175@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing External Interrupts and Traps, Interrupt Processing
176@end ifinfo
177@section Interrupt Levels
178
179Two levels (enabled and disabled) of interrupt
180priorities are supported by the PA-RISC architecture.  Level
181zero (0) indicates that interrupts are fully enabled (i.e. the I
182bit of the PSW is 1).  Level one (1) indicates that interrupts
183are disabled (i.e. the I bit of the PSW is 0).  Thirty-two
184independent sources of external interrupts are supported by the
185PA-RISC architecture.  Each of these interrupts sources may be
186individually enabled or disabled.  When processor interrupts are
187disabled, all sources of external interrupts are ignored.  When
188processor interrupts are enabled, the EIR (External Interrupt
189Request) register is used to determine which sources are
190currently allowed to generate interrupts.
191
192Although RTEMS supports 256 interrupt levels, the
193PA-RISC architecture only supports two.  RTEMS interrupt level 0
194indicates that interrupts are enabled and level 1 indicates that
195interrupts are disabled.  All other RTEMS interrupt levels are
196undefined and their behavior is unpredictable.
197
198@ifinfo
199@node Interrupt Processing Disabling of Interrupts by RTEMS, Default Fatal Error Processing, Interrupt Processing Interrupt Levels, Interrupt Processing
200@end ifinfo
201@section Disabling of Interrupts by RTEMS
202
203During the execution of directive calls, critical
204sections of code may be executed.  When these sections are
205encountered, RTEMS disables external interrupts by setting the I
206bit in the PSW to 0 before the execution of this section and
207restores them to the previous level upon completion of the
208section.  RTEMS has been optimized to insure that interrupts are
209disabled for less than XXX instructions when compiled with GNU
210CC at optimization level 4.  The exact execution time will vary
211based on the based on the processor implementation, amount of
212cache, the number of wait states for primary memory, and
213processor speed present on the target board.
214
215Non-maskable interrupts (NMI) such as high-priority
216machine checks cannot be disabled, and ISRs which execute at
217this level MUST NEVER issue RTEMS system calls.  If a directive
218is invoked, unpredictable results may occur due to the inability
219of RTEMS to protect its critical sections.  However, ISRs that
220make no system calls may safely execute as non-maskable
221interrupts.
222
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