1 | @c |
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2 | @c COPYRIGHT (c) 1988-1997. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | |
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7 | @ifinfo |
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8 | @node Default Fatal Error Processing, Default Fatal Error Processing Introduction, Interrupt Processing Disabling of Interrupts by RTEMS, Top |
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9 | @end ifinfo |
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10 | @chapter Default Fatal Error Processing |
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11 | @ifinfo |
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12 | @menu |
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13 | * Default Fatal Error Processing Introduction:: |
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14 | * Default Fatal Error Processing Default Fatal Error Handler Operations:: |
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15 | @end menu |
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16 | @end ifinfo |
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17 | |
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18 | @ifinfo |
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19 | @node Default Fatal Error Processing Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Default Fatal Error Processing, Default Fatal Error Processing |
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20 | @end ifinfo |
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21 | @section Introduction |
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22 | |
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23 | Upon detection of a fatal error by either the |
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24 | application or RTEMS the fatal error manager is invoked. The |
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25 | fatal error manager will invoke a user-supplied fatal error |
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26 | handler. If no user-supplied handler is configured, the RTEMS |
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27 | provided default fatal error handler is invoked. If the |
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28 | user-supplied fatal error handler returns to the executive the |
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29 | default fatal error handler is then invoked. This chapter |
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30 | describes the precise operations of the default fatal error |
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31 | handler. |
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32 | |
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33 | @ifinfo |
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34 | @node Default Fatal Error Processing Default Fatal Error Handler Operations, Board Support Packages, Default Fatal Error Processing Introduction, Default Fatal Error Processing |
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35 | @end ifinfo |
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36 | @section Default Fatal Error Handler Operations |
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37 | |
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38 | The default fatal error handler which is invoked by |
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39 | the fatal_error_occurred directive when there is no user handler |
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40 | configured or the user handler returns control to RTEMS. The |
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41 | default fatal error handler disables processor interrupts (i.e. |
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42 | sets the I bit in the PSW register to 0), places the error code |
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43 | in r1, and executes a break instruction to simulate a halt |
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44 | processor instruction. |
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45 | |
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