1 | @c |
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2 | @c COPYRIGHT (c) 1988-1999. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @chapter CPU Model Dependent Features |
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10 | |
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11 | @section Introduction |
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12 | |
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13 | Microprocessors are generally classified into |
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14 | families with a variety of CPU models or implementations within |
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15 | that family. Within a processor family, there is a high level |
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16 | of binary compatibility. This family may be based on either an |
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17 | architectural specification or on maintaining compatibility with |
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18 | a popular processor. Recent microprocessor families such as the |
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19 | SPARC or PowerPC are based on an architectural specification |
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20 | which is independent or any particular CPU model or |
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21 | implementation. Older families such as the M68xxx and the iX86 |
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22 | evolved as the manufacturer strived to produce higher |
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23 | performance processor models which maintained binary |
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24 | compatibility with older models. |
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25 | |
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26 | RTEMS takes advantage of the similarity of the |
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27 | various models within a CPU family. Although the models do vary |
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28 | in significant ways, the high level of compatibility makes it |
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29 | possible to share the bulk of the CPU dependent executive code |
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30 | across the entire family. Each processor family supported by |
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31 | RTEMS has a list of features which vary between CPU models |
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32 | within a family. For example, the most common model dependent |
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33 | feature regardless of CPU family is the presence or absence of a |
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34 | floating point unit or coprocessor. When defining the list of |
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35 | features present on a particular CPU model, one simply notes |
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36 | that floating point hardware is or is not present and defines a |
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37 | single constant appropriately. Conditional compilation is |
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38 | utilized to include the appropriate source code for this CPU |
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39 | model's feature set. It is important to note that this means |
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40 | that RTEMS is thus compiled using the appropriate feature set |
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41 | and compilation flags optimal for this CPU model used. The |
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42 | alternative would be to generate a binary which would execute on |
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43 | all family members using only the features which were always |
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44 | present. |
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45 | |
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46 | This chapter presents the set of features which vary |
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47 | across the various implementations of the C3x/C4x architecture |
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48 | that are of importance to rtems. |
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49 | the set of cpu model feature macros are defined in the file |
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50 | cpukit/score/cpu/c4x/rtems/score/c4x.h and are based upon |
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51 | the particular cpu model defined in the bsp's custom configuration |
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52 | file as well as the compilation command line. |
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53 | |
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54 | @section CPU Model Name |
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55 | |
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56 | The macro @code{CPU_MODEL_NAME} is a string which designates |
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57 | the name of this cpu model. for example, for the c32 |
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58 | processor, this macro is set to the string "c32". |
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59 | |
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60 | @section Floating Point Unit |
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61 | |
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62 | The Texas Instruments C3x/C4x family makes little distinction |
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63 | between the various cpu registers. Although floating point |
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64 | operations may only be performed on a subset of the cpu registers, |
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65 | these same registers may be used for normal integer operations. |
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66 | as a result of this, this port of rtems makes no distinction |
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67 | between integer and floating point contexts. The routine |
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68 | @code{_CPU_Context_switch} saves all of the registers that |
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69 | comprise a task's context. the routines that initialize, |
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70 | save, and restore floating point contexts are not present |
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71 | in this port. |
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72 | |
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73 | Moreover, there is no floating point context pointer and |
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74 | the code in @code{_Thread_Dispatch} that manages the |
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75 | floating point context switching process is disabled |
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76 | on this port. |
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77 | |
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78 | This not only simplifies the port, it also speeds up context |
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79 | switches by reducing the code involved and reduces the code |
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80 | space footprint of the executive on the Texas Instruments |
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81 | C3x/C4x. |
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82 | |
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