1 | @c |
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2 | @c Interrupt Stack Frame Picture |
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3 | @c |
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4 | @c COPYRIGHT (c) 1988-2002. |
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5 | @c On-Line Applications Research Corporation (OAR). |
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6 | @c All rights reserved. |
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7 | @c |
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8 | @c $Id$ |
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9 | @c |
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10 | |
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11 | @chapter Interrupt Processing |
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12 | |
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13 | @section Introduction |
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14 | |
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15 | Different types of processors respond to the |
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16 | occurrence of an interrupt in its own unique fashion. In |
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17 | addition, each processor type provides a control mechanism to |
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18 | allow for the proper handling of an interrupt. The processor |
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19 | dependent response to the interrupt modifies the current |
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20 | execution state and results in a change in the execution stream. |
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21 | Most processors require that an interrupt handler utilize some |
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22 | special control mechanisms to return to the normal processing |
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23 | stream. Although RTEMS hides many of the processor dependent |
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24 | details of interrupt processing, it is important to understand |
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25 | how the RTEMS interrupt manager is mapped onto the processor's |
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26 | unique architecture. Discussed in this chapter are the ARM's |
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27 | interrupt response and control mechanisms as they pertain to |
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28 | RTEMS. |
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29 | |
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30 | The ARM has 7 exception types: |
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31 | @itemize @bullet |
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32 | |
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33 | @item Reset |
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34 | @item Undefined instruction |
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35 | @item Software interrupt (SWI) |
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36 | @item Prefetch Abort |
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37 | @item Data Abort |
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38 | @item Interrupt (IRQ) |
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39 | @item Fast Interrupt (FIQ) |
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40 | |
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41 | @end itemize |
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42 | |
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43 | Of these types, only IRQ and FIQ are handled through RTEMS's interrupt |
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44 | vectoring. |
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45 | |
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46 | @section Vectoring of an Interrupt Handler |
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47 | |
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48 | |
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49 | Unlike many other architectures, the ARM has seperate stacks for each |
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50 | interrupt. When the CPU receives an interrupt, it: |
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51 | |
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52 | @itemize @bullet |
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53 | @item switches to the exception mode corresponding to the interrupt, |
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54 | |
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55 | @item saves the Current Processor Status Register (CPSR) to the |
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56 | exception mode's Saved Processor Status Register (SPSR), |
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57 | |
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58 | @item masks off the IRQ and if the interrupt source was FIQ, the FIQ |
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59 | is masked off as well, |
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60 | |
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61 | @item saves the Program Counter (PC) to the exception mode's Link |
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62 | Register (LR - same as R14), |
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63 | |
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64 | @item and sets the PC to the exception's vector address. |
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65 | |
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66 | @end itemize |
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67 | |
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68 | The vectors for both IRQ and FIQ point to the _ISR_Handler function. |
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69 | _ISR_Handler() calls the BSP specific handler, ExecuteITHandler(). Before |
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70 | calling ExecuteITHandler(), registers R0-R3, R12, and R14(LR) are saved so |
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71 | that it is safe to call C functions. Even ExecuteITHandler() can be written |
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72 | in C. |
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73 | |
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74 | @section Interrupt Levels |
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75 | |
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76 | The ARM architecture supports two external interrupts - IRQ and FIQ. FIQ |
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77 | has a higher priority than IRQ, and has its own version of register R8 - R14, |
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78 | however RTEMS does not take advantage of them. Both interrupts are enabled |
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79 | through the CPSR. |
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80 | |
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81 | The RTEMS interrupt level mapping scheme for the AEM is not a numeric level |
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82 | as on most RTEMS ports. It is a bit mapping that corresponds the enable |
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83 | bits's postions in the CPSR: |
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84 | |
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85 | @table @b |
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86 | @item FIQ |
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87 | Setting bit 6 (0 is least significant bit) disables the FIQ. |
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88 | |
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89 | @item IRQ |
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90 | Setting bit 7 (0 is least significant bit) disables the IRQ. |
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91 | |
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92 | @end table |
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93 | |
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94 | |
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95 | @section Disabling of Interrupts by RTEMS |
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96 | |
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97 | During the execution of directive calls, critical |
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98 | sections of code may be executed. When these sections are |
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99 | encountered, RTEMS disables interrupts to level seven (7) before |
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100 | the execution of this section and restores them to the previous |
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101 | level upon completion of the section. RTEMS has been optimized |
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102 | to insure that interrupts are disabled for less than |
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103 | RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a |
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104 | RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor with |
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105 | zero wait states. These numbers will vary based the |
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106 | number of wait states and processor speed present on the target board. |
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107 | [NOTE: The maximum period with interrupts disabled is hand calculated. This |
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108 | calculation was last performed for Release |
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109 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
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110 | |
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111 | Non-maskable interrupts (NMI) cannot be disabled, and |
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112 | ISRs which execute at this level MUST NEVER issue RTEMS system |
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113 | calls. If a directive is invoked, unpredictable results may |
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114 | occur due to the inability of RTEMS to protect its critical |
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115 | sections. However, ISRs that make no system calls may safely |
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116 | execute as non-maskable interrupts. |
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117 | |
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118 | @section Interrupt Stack |
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119 | |
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120 | RTEMS expects the interrupt stacks to be set up in bsp_start(). The memory |
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121 | for the stacks is reserved in the linker script. |
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122 | |
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