source: rtems/doc/supplements/arm/bsp.t @ 8d7393a

4.104.114.84.9
Last change on this file since 8d7393a was 8d7393a, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 30, 2002 at 9:43:53 PM

2002-07-30 Joel Sherrill <joel@…>

  • BSP_TIMES, ChangeLog?, Makefile.am, arm.texi, bsp.t, callconv.t, cpumodel.t, cputable.t, fatalerr.t, intr_NOTIMES.t, memmodel.t, preface.texi, stamp-vti, timeBSP.t, timing.texi, version.texi, wksheets.texi: New files as ARM supplement initial version added.
  • Property mode set to 100644
File size: 3.1 KB
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1@c
2@c  COPYRIGHT (c) 1988-2002.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5@c
6@c  $Id$
7@c
8
9@chapter Board Support Packages
10
11@section Introduction
12
13An RTEMS Board Support Package (BSP) must be designed
14to support a particular processor and target board combination.
15This chapter presents a discussion of XXX specific BSP
16issues.   For more information on developing a BSP, refer to the
17chapter titled Board Support Packages in the RTEMS
18Applications User's Guide.
19
20@section System Reset
21
22An RTEMS based application is initiated or
23re-initiated when the XXX processor is reset.  When the
24XXX is reset, the processor performs the following actions:
25
26@itemize @bullet
27@item The tracing bits of the status register are cleared to
28disable tracing.
29
30@item The supervisor interrupt state is entered by setting the
31supervisor (S) bit and clearing the master/interrupt (M) bit of
32the status register.
33
34@item The interrupt mask of the status register is set to
35level 7 to effectively disable all maskable interrupts.
36
37@item The vector base register (VBR) is set to zero.
38
39@item The cache control register (CACR) is set to zero to
40disable and freeze the processor cache.
41
42@item The interrupt stack pointer (ISP) is set to the value
43stored at vector 0 (bytes 0-3) of the exception vector table
44(EVT).
45
46@item The program counter (PC) is set to the value stored at
47vector 1 (bytes 4-7) of the EVT.
48
49@item The processor begins execution at the address stored in
50the PC.
51@end itemize
52
53@section Processor Initialization
54
55The address of the application's initialization code
56should be stored in the first vector of the EVT which will allow
57the immediate vectoring to the application code.  If the
58application requires that the VBR be some value besides zero,
59then it should be set to the required value at this point.  All
60tasks share the same XXX's VBR value.  Because interrupts
61are enabled automatically by RTEMS as part of the initialize
62executive directive, the VBR MUST be set before this directive
63is invoked to insure correct interrupt vectoring.  If processor
64caching is to be utilized, then it should be enabled during the
65reset application initialization code.
66
67In addition to the requirements described in the
68Board Support Packages chapter of the Applications User's
69Manual for the reset code which is executed before the call to
70initialize executive, the XXX version has the following
71specific requirements:
72
73@itemize @bullet
74@item Must leave the S bit of the status register set so that
75the XXX remains in the supervisor state.
76
77@item Must set the M bit of the status register to remove the
78XXX from the interrupt state.
79
80@item Must set the master stack pointer (MSP) such that a
81minimum stack size of MINIMUM_STACK_SIZE bytes is provided for
82the initialize executive directive.
83
84@item Must initialize the XXX's vector table.
85@end itemize
86
87Note that the BSP is not responsible for allocating
88or installing the interrupt stack.  RTEMS does this
89automatically as part of initialization.  If the BSP does not
90install an interrupt stack and -- for whatever reason -- an
91interrupt occurs before initialize_executive is invoked, then
92the results are unpredictable.
93
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