source: rtems/doc/networking/decdriver.t @ ec95bd8

4.104.114.84.95
Last change on this file since ec95bd8 was ec95bd8, checked in by Ralf Corsepius <ralf.corsepius@…>, on Jul 31, 2004 at 3:10:08 AM

2004-07-31 Ralf Corsepius <ralf_corsepius@…>

  • networking/networkflow.txt, networking/PCIreg.txt, networking/recvbd.txt: New.
  • networking/decdriver.t, networking/networktasks.t: Use @image for ASCII figures (Reflect changes above).
  • Property mode set to 100644
File size: 10.5 KB
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1@c
2@c  RTEMS Remote Debugger Server Specifications
3@c
4@c  Written by: Emmanuel Raguet <raguet@crf.canon.fr>
5@c
6@c
7@c  $Id$
8@c
9
10@chapter DEC 21140 Driver
11
12@section DEC 21240 Driver Introduction
13
14@c XXX add back in cross reference to list of boards.
15
16One aim of our project is to port RTEMS on a standard PowerPC platform.
17To achieve it, we have chosen a Motorola MCP750 board. This board includes
18an Ethernet controller based on a DEC21140 chip. Because RTEMS has a
19TCP/IP stack, we will
20have to develop the DEC21140 related ethernet driver for the PowerPC port of
21RTEMS. As this controller is able to support 100Mbps network and as there is
22a lot of PCI card using this DEC chip, we have decided to first
23implement this driver on an Intel PC386 target to provide a solution for using
24RTEMS on PC with the 100Mbps network and then to port this code on PowerPC in
25a second phase.
26
27
28The aim of this document is to give some PCI board generalities and
29to explain the software architecture of the RTEMS driver. Finally, we will see
30what will be done for ChorusOs and Netboot environment .
31
32
33@section Document Revision History
34
35@b{Current release}:
36
37@itemize @bullet
38@item Current applicable release is 1.0.
39@end itemize
40@b{Existing releases}:
41
42@itemize @bullet
43@item 1.0 : Released the 10/02/98. First version of this document.
44@item 0.1 : First draft of this document
45@end itemize
46@b{Planned releases}:
47
48@itemize @bullet
49@item None planned today.
50@end itemize
51
52@section DEC21140 PCI Board Generalities
53
54@c XXX add crossreference to PCI Register Figure
55This chapter describes rapidely the PCI interface of this Ethernet controller.
56The board we have chosen for our PC386 implementation is a D-Link DFE-500TX.
57This is a dual-speed 10/100Mbps Ethernet PCI adapter with a DEC21140AF chip.
58Like other PCI devices, this board has a PCI device's header containing some
59required configuration registers, as shown in the PCI Register Figure.
60By reading
61or writing these registers, a driver can obtain information about the type of
62the board, the interrupt it uses, the mapping of the chip specific registers, ...
63
64
65
66On Intel target, the chip specific registers can be accessed via 2
67methods : I/O port access or PCI address mapped access. We have chosen to implement
68the PCI address access to obtain compatible source code to the port the driver
69on a PowerPC target.
70
71@c
72@c PCI Device's Configuration Header Space Format
73@c
74
75@ifclear use-html
76@image{PCIreg,,,PCI Device's Configuration Header Space Format}
77@end ifclear
78
79@ifset use-html
80@c <IMG SRC="PCIreg.jpg" WIDTH=500 HEIGHT=600 ALT="PCI Device's Configuration Header Space Format">
81@html
82 <IMG SRC="PCIreg.jpg" ALT="PCI Device's Configuration Header Space Format">
83@end html
84@end ifset
85
86
87@c XXX add crossreference to PCI Register Figure
88
89On RTEMS, a PCI API exists. We have used it to configure the board. After initializing
90this PCI module via the @code{pcib_init()} function, we try to detect
91the DEC21140 based ethernet board. This board is characterized by its Vendor
92ID (0x1011) and its Device ID (0x0009). We give these arguments to the
93@code{pcib_find_by_deviceid}
94function which returns , if the device is present, a pointer to the configuration
95header space (see PCI Registers Fgure). Once this operation performed,
96the driver
97is able to extract the information it needs to configure the board internal
98registers, like the interrupt line, the base address,... The board internal
99registers will not be detailled here. You can find them in @b{DIGITAL
100Semiconductor 21140A PCI Fast Ethernet LAN Controller
101- Hardware Reference Manual}.
102
103@c fix citation
104
105
106@section RTEMS Driver Software Architecture
107
108In this chapter will see the initialization phase, how the controller uses the
109host memory and the 2 threads launched at the initialization time.
110
111
112@subsection Initialization phase
113
114The DEC21140 Ethernet driver keeps the same software architecture than the other
115RTEMS ethernet drivers. The only API the programmer can use is the @code{rtems_dec21140_driver_attach}
116@code{(struct rtems_bsdnet_ifconfig *config)} function which
117detects the board and initializes the associated data structure (with registers
118base address, entry points to low-level initialization function,...), if the
119board is found.
120
121Once the attach function executed, the driver initializes the DEC
122chip. Then the driver connects an interrupt handler to the interrupt line driven
123by the Ethernet controller (the only interrupt which will be treated is the
124receive interrupt) and launches 2 threads : a receiver thread and a transmitter
125thread. Then the driver waits for incoming frame to give to the protocol stack
126or outcoming frame to send on the physical link.
127
128
129@subsection Memory Buffer
130
131@c XXX add cross reference to Problem
132This DEC chip uses the host memory to store the incoming Ethernet frames and
133the descriptor of these frames. We have chosen to use 7 receive buffers and
1341 transmit buffer to optimize memory allocation due to cache and paging problem
135that will be explained in the section @b{Encountered Problems}.
136
137
138To reference these buffers to the DEC chip we use a buffer descriptors
139ring. The descriptor structure is defined in the Buffer Descriptor Figure.
140Each descriptor
141can reference one or two memory buffers. We choose to use only one buffer of
1421520 bytes per descriptor.
143
144
145The difference between a receive and a transmit buffer descriptor
146is located in the status and control bits fields. We do not give details here,
147please refer to the [DEC21140 Hardware Manual].
148
149@c
150@c Buffer Descriptor
151@c
152
153@ifclear use-html
154@image{recvbd,,,"Buffer Descriptor"}
155@end ifclear
156
157@ifset use-html
158@c <IMG SRC="recvbd.jpg" WIDTH=500 HEIGHT=600 ALT="Buffer Descriptor">
159@html
160<IMG SRC="recvbd.jpg" ALT="Buffer Descriptor">
161@end html
162@end ifset
163
164
165
166@subsection Receiver Thread
167
168This thread is event driven. Each time a DEC PCI board interrupt occurs, the
169handler checks if this is a receive interrupt and send an event ``reception''
170to the receiver thread which looks into the entire buffer descriptors ring the
171ones that contain a valid incoming frame (bit OWN=0 means descriptor belongs
172to host processor). Each valid incoming ethernet frame is sent to the protocol
173stack and the buffer descriptor is given back to the DEC board (the host processor
174reset bit OWN, which means descriptor belongs to 21140).
175
176
177@subsection Transmitter Thread
178
179This thread is also event driven. Each time an Ethernet frame is put in the
180transmit queue, an event is sent to the transmit thread, which empty the queue
181by sending each outcoming frame. Because we use only one transmit buffer, we
182are sure that the frame is well-sent before sending the next.
183
184
185@section Encountered Problems
186
187On Intel PC386 target, we were faced with a problem of memory cache management.
188Because the DEC chip uses the host memory to store the incoming frame and because
189the DEC21140 configuration registers are mapped into the PCI address space,
190we must ensure that the data read (or written) by the host processor are the
191ones written (or read) by the DEC21140 device in the host memory and not old
192data stored in the cache memory. Therefore, we had to provide a way to manage
193the cache. This module is described in the document @b{RTEMS
194Cache Management For Intel}. On Intel, the
195memory region cache management is available only if the paging unit is enabled.
196We have used this paging mechanism, with 4Kb page. All the buffers allocated
197to store the incoming or outcoming frames, buffer descriptor and also the PCI
198address space of the DEC board are located in a memory space with cache disable.
199
200
201Concerning the buffers and their descriptors, we have tried to optimize
202the memory space in term of allocated page. One buffer has 1520 bytes, one descriptor
203has 16 bytes. We have 7 receive buffers and 1 transmit buffer, and for each,
2041 descriptor : (7+1)*(1520+16) = 12288 bytes = 12Kb = 3 entire pages. This
205allows not to lose too much memory or not to disable cache memory for a page
206which contains other data than buffer, which could decrease performance.
207
208
209@section ChorusOs DEC Driver
210
211Because ChorusOs is used in several Canon CRF projects, we must provide such
212a driver on this OS to ensure compatibility between the RTEMS and ChorusOs developments.
213On ChorusOs, a DEC driver source code already exists but only for a PowerPC
214target. We plan to port this code (which uses ChorusOs API) on Intel target.
215This will allow us to have homogeneous developments. Moreover, the port of the
216development performed with ChorusOs environment to RTEMS environment will be
217easier for the developers.
218
219
220@section Netboot DEC driver
221
222We use Netboot tool to load our development from a server to the target via
223an ethernet network. Currently, this tool does not support the DEC board. We
224plan to port the DEC driver for the Netboot tool.
225
226
227But concerning the port of the DEC driver into Netboot, we are faced
228with a problem : in RTEMS environment, the DEC driver is interrupt or event
229driven, in Netboot environment, it must be used in polling mode. It means that
230we will have to re-write some mechanisms of this driver.
231
232
233@section List of Ethernet cards using the DEC chip
234
235Many Ethernet adapter cards use the Tulip chip. Here is a non exhaustive list
236of adapters which support this driver :
237
238@itemize @bullet
239@item Accton EtherDuo PCI.
240@item Accton EN1207 All three media types supported.
241@item Adaptec ANA6911/TX 21140-AC.
242@item Cogent EM110 21140-A with DP83840 N-Way MII transceiver.
243@item Cogent EM400 EM100 with 4 21140 100mbps-only ports + PCI Bridge.
244@item Danpex EN-9400P3.
245@item D-Link DFE500-Tx 21140-A with DP83840 transceiver.
246@item Kingston EtherX KNE100TX 21140AE.
247@item Netgear FX310 TX 10/100 21140AE.
248@item SMC EtherPower10/100 With DEC21140 and 68836 SYM transceiver.
249@item SMC EtherPower10/100 With DEC21140-AC and DP83840 MII transceiver.
250Note: The EtherPower II uses the EPIC chip, which requires a different driver.
251@item Surecom EP-320X DEC 21140.
252@item Thomas Conrad TC5048.
253@item Znyx ZX345 21140-A, usually with the DP83840 N-Way MII transciever. Some ZX345
254cards made in 1996 have an ICS 1890 transciver instead.
255@item ZNYX ZX348 Two 21140-A chips using ICS 1890 transcievers and either a 21052
256or 21152 bridge. Early versions used National 83840 transcievers, but later
257versions are depopulated ZX346 boards.
258@item ZNYX ZX351 21140 chip with a Broadcom 100BaseT4 transciever.
259@end itemize
260
261Our DEC driver has not been tested with all these cards, only with the D-Link
262DFE500-TX.
263
264@itemize @code{ }
265@item @cite{[DEC21140 Hardware Manual] DIGITAL, @b{DIGITAL
266Semiconductor 21140A PCI Fast Ethernet LAN Controller - Hardware
267Reference Manual}}.
268
269@item @cite{[99.TA.0021.M.ER]Emmanuel Raguet,
270@b{RTEMS Cache Management For Intel}}.
271@end itemize
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