[5dbc2e2] | 1 | @c |
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| 2 | @c RTEMS Remote Debugger Server Specifications |
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| 3 | @c |
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| 4 | @c Written by: Emmanuel Raguet <raguet@crf.canon.fr> |
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| 5 | @c |
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| 6 | @c |
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| 7 | @c $Id$ |
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| 8 | @c |
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| 9 | |
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[936ae5d] | 10 | @chapter DEC 21140 Driver |
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[5dbc2e2] | 11 | |
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[936ae5d] | 12 | @section DEC 21240 Driver Introduction |
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[5dbc2e2] | 13 | |
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| 14 | @c XXX add back in cross reference to list of boards. |
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| 15 | |
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[1750364c] | 16 | One aim of our project is to port RTEMS on a standard PowerPC platform. |
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| 17 | To achieve it, we have chosen a Motorola MCP750 board. This board includes |
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| 18 | an Ethernet controller based on a DEC21140 chip. Because RTEMS has a |
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| 19 | TCP/IP stack, we will |
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[5dbc2e2] | 20 | have to develop the DEC21140 related ethernet driver for the PowerPC port of |
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| 21 | RTEMS. As this controller is able to support 100Mbps network and as there is |
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| 22 | a lot of PCI card using this DEC chip, we have decided to first |
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| 23 | implement this driver on an Intel PC386 target to provide a solution for using |
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| 24 | RTEMS on PC with the 100Mbps network and then to port this code on PowerPC in |
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| 25 | a second phase. |
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| 26 | |
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| 27 | |
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| 28 | The aim of this document is to give some PCI board generalities and |
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| 29 | to explain the software architecture of the RTEMS driver. Finally, we will see |
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| 30 | what will be done for ChorusOs and Netboot environment . |
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| 31 | |
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| 32 | |
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| 33 | @section Document Revision History |
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| 34 | |
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| 35 | @b{Current release}: |
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| 36 | |
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| 37 | @itemize @bullet |
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| 38 | @item Current applicable release is 1.0. |
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| 39 | @end itemize |
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| 40 | @b{Existing releases}: |
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| 41 | |
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| 42 | @itemize @bullet |
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| 43 | @item 1.0 : Released the 10/02/98. First version of this document. |
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| 44 | @item 0.1 : First draft of this document |
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| 45 | @end itemize |
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| 46 | @b{Planned releases}: |
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| 47 | |
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| 48 | @itemize @bullet |
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| 49 | @item None planned today. |
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| 50 | @end itemize |
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| 51 | |
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| 52 | @section DEC21140 PCI Board Generalities |
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| 53 | |
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| 54 | @c XXX add crossreference to PCI Register Figure |
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| 55 | This chapter describes rapidely the PCI interface of this Ethernet controller. |
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| 56 | The board we have chosen for our PC386 implementation is a D-Link DFE-500TX. |
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| 57 | This is a dual-speed 10/100Mbps Ethernet PCI adapter with a DEC21140AF chip. |
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| 58 | Like other PCI devices, this board has a PCI device's header containing some |
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| 59 | required configuration registers, as shown in the PCI Register Figure. |
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| 60 | By reading |
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| 61 | or writing these registers, a driver can obtain information about the type of |
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| 62 | the board, the interrupt it uses, the mapping of the chip specific registers, ... |
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| 63 | |
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| 64 | |
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| 65 | |
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| 66 | On Intel target, the chip specific registers can be accessed via 2 |
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| 67 | methods : I/O port access or PCI address mapped access. We have chosen to implement |
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| 68 | the PCI address access to obtain compatible source code to the port the driver |
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| 69 | on a PowerPC target. |
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| 70 | |
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| 71 | @c |
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| 72 | @c PCI Device's Configuration Header Space Format |
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| 73 | @c |
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| 74 | |
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[ec95bd8] | 75 | @ifclear use-html |
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| 76 | @image{PCIreg,,,PCI Device's Configuration Header Space Format} |
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| 77 | @end ifclear |
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[5dbc2e2] | 78 | |
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| 79 | @ifset use-html |
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[dbba80a9] | 80 | @c <IMG SRC="PCIreg.jpg" WIDTH=500 HEIGHT=600 ALT="PCI Device's Configuration Header Space Format"> |
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[5dbc2e2] | 81 | @html |
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[ec95bd8] | 82 | <IMG SRC="PCIreg.jpg" ALT="PCI Device's Configuration Header Space Format"> |
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[5dbc2e2] | 83 | @end html |
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| 84 | @end ifset |
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| 85 | |
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| 86 | |
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| 87 | @c XXX add crossreference to PCI Register Figure |
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| 88 | |
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| 89 | On RTEMS, a PCI API exists. We have used it to configure the board. After initializing |
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| 90 | this PCI module via the @code{pcib_init()} function, we try to detect |
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| 91 | the DEC21140 based ethernet board. This board is characterized by its Vendor |
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| 92 | ID (0x1011) and its Device ID (0x0009). We give these arguments to the |
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| 93 | @code{pcib_find_by_deviceid} |
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| 94 | function which returns , if the device is present, a pointer to the configuration |
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| 95 | header space (see PCI Registers Fgure). Once this operation performed, |
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| 96 | the driver |
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| 97 | is able to extract the information it needs to configure the board internal |
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| 98 | registers, like the interrupt line, the base address,... The board internal |
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[936ae5d] | 99 | registers will not be detailled here. You can find them in @b{DIGITAL |
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[5dbc2e2] | 100 | Semiconductor 21140A PCI Fast Ethernet LAN Controller |
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| 101 | - Hardware Reference Manual}. |
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| 102 | |
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| 103 | @c fix citation |
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| 104 | |
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| 105 | |
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| 106 | @section RTEMS Driver Software Architecture |
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| 107 | |
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| 108 | In this chapter will see the initialization phase, how the controller uses the |
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| 109 | host memory and the 2 threads launched at the initialization time. |
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| 110 | |
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| 111 | |
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| 112 | @subsection Initialization phase |
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| 113 | |
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| 114 | The DEC21140 Ethernet driver keeps the same software architecture than the other |
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| 115 | RTEMS ethernet drivers. The only API the programmer can use is the @code{rtems_dec21140_driver_attach} |
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| 116 | @code{(struct rtems_bsdnet_ifconfig *config)} function which |
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| 117 | detects the board and initializes the associated data structure (with registers |
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| 118 | base address, entry points to low-level initialization function,...), if the |
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| 119 | board is found. |
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| 120 | |
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| 121 | Once the attach function executed, the driver initializes the DEC |
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| 122 | chip. Then the driver connects an interrupt handler to the interrupt line driven |
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| 123 | by the Ethernet controller (the only interrupt which will be treated is the |
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| 124 | receive interrupt) and launches 2 threads : a receiver thread and a transmitter |
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| 125 | thread. Then the driver waits for incoming frame to give to the protocol stack |
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| 126 | or outcoming frame to send on the physical link. |
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| 127 | |
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| 128 | |
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| 129 | @subsection Memory Buffer |
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| 130 | |
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| 131 | @c XXX add cross reference to Problem |
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| 132 | This DEC chip uses the host memory to store the incoming Ethernet frames and |
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| 133 | the descriptor of these frames. We have chosen to use 7 receive buffers and |
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| 134 | 1 transmit buffer to optimize memory allocation due to cache and paging problem |
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[936ae5d] | 135 | that will be explained in the section @b{Encountered Problems}. |
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[5dbc2e2] | 136 | |
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| 137 | |
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| 138 | To reference these buffers to the DEC chip we use a buffer descriptors |
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| 139 | ring. The descriptor structure is defined in the Buffer Descriptor Figure. |
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| 140 | Each descriptor |
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| 141 | can reference one or two memory buffers. We choose to use only one buffer of |
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| 142 | 1520 bytes per descriptor. |
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| 143 | |
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| 144 | |
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| 145 | The difference between a receive and a transmit buffer descriptor |
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| 146 | is located in the status and control bits fields. We do not give details here, |
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| 147 | please refer to the [DEC21140 Hardware Manual]. |
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| 148 | |
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| 149 | @c |
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| 150 | @c Buffer Descriptor |
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| 151 | @c |
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| 152 | |
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[ec95bd8] | 153 | @ifclear use-html |
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| 154 | @image{recvbd,,,"Buffer Descriptor"} |
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| 155 | @end ifclear |
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[5dbc2e2] | 156 | |
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| 157 | @ifset use-html |
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[154f0a3] | 158 | @c <IMG SRC="recvbd.jpg" WIDTH=500 HEIGHT=600 ALT="Buffer Descriptor"> |
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[5dbc2e2] | 159 | @html |
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[154f0a3] | 160 | <IMG SRC="recvbd.jpg" ALT="Buffer Descriptor"> |
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[5dbc2e2] | 161 | @end html |
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| 162 | @end ifset |
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| 163 | |
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| 164 | |
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| 165 | |
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| 166 | @subsection Receiver Thread |
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| 167 | |
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| 168 | This thread is event driven. Each time a DEC PCI board interrupt occurs, the |
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| 169 | handler checks if this is a receive interrupt and send an event ``reception'' |
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| 170 | to the receiver thread which looks into the entire buffer descriptors ring the |
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| 171 | ones that contain a valid incoming frame (bit OWN=0 means descriptor belongs |
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| 172 | to host processor). Each valid incoming ethernet frame is sent to the protocol |
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| 173 | stack and the buffer descriptor is given back to the DEC board (the host processor |
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| 174 | reset bit OWN, which means descriptor belongs to 21140). |
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| 175 | |
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| 176 | |
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| 177 | @subsection Transmitter Thread |
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| 178 | |
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| 179 | This thread is also event driven. Each time an Ethernet frame is put in the |
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| 180 | transmit queue, an event is sent to the transmit thread, which empty the queue |
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| 181 | by sending each outcoming frame. Because we use only one transmit buffer, we |
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| 182 | are sure that the frame is well-sent before sending the next. |
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| 183 | |
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| 184 | |
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| 185 | @section Encountered Problems |
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| 186 | |
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| 187 | On Intel PC386 target, we were faced with a problem of memory cache management. |
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| 188 | Because the DEC chip uses the host memory to store the incoming frame and because |
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| 189 | the DEC21140 configuration registers are mapped into the PCI address space, |
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| 190 | we must ensure that the data read (or written) by the host processor are the |
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| 191 | ones written (or read) by the DEC21140 device in the host memory and not old |
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| 192 | data stored in the cache memory. Therefore, we had to provide a way to manage |
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| 193 | the cache. This module is described in the document @b{RTEMS |
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| 194 | Cache Management For Intel}. On Intel, the |
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| 195 | memory region cache management is available only if the paging unit is enabled. |
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| 196 | We have used this paging mechanism, with 4Kb page. All the buffers allocated |
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| 197 | to store the incoming or outcoming frames, buffer descriptor and also the PCI |
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| 198 | address space of the DEC board are located in a memory space with cache disable. |
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| 199 | |
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| 200 | |
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| 201 | Concerning the buffers and their descriptors, we have tried to optimize |
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| 202 | the memory space in term of allocated page. One buffer has 1520 bytes, one descriptor |
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| 203 | has 16 bytes. We have 7 receive buffers and 1 transmit buffer, and for each, |
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| 204 | 1 descriptor : (7+1)*(1520+16) = 12288 bytes = 12Kb = 3 entire pages. This |
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| 205 | allows not to lose too much memory or not to disable cache memory for a page |
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| 206 | which contains other data than buffer, which could decrease performance. |
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| 207 | |
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| 208 | |
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| 209 | @section ChorusOs DEC Driver |
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| 210 | |
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| 211 | Because ChorusOs is used in several Canon CRF projects, we must provide such |
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| 212 | a driver on this OS to ensure compatibility between the RTEMS and ChorusOs developments. |
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| 213 | On ChorusOs, a DEC driver source code already exists but only for a PowerPC |
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| 214 | target. We plan to port this code (which uses ChorusOs API) on Intel target. |
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| 215 | This will allow us to have homogeneous developments. Moreover, the port of the |
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| 216 | development performed with ChorusOs environment to RTEMS environment will be |
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| 217 | easier for the developers. |
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| 218 | |
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| 219 | |
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| 220 | @section Netboot DEC driver |
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| 221 | |
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| 222 | We use Netboot tool to load our development from a server to the target via |
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| 223 | an ethernet network. Currently, this tool does not support the DEC board. We |
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| 224 | plan to port the DEC driver for the Netboot tool. |
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| 225 | |
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| 226 | |
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| 227 | But concerning the port of the DEC driver into Netboot, we are faced |
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| 228 | with a problem : in RTEMS environment, the DEC driver is interrupt or event |
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| 229 | driven, in Netboot environment, it must be used in polling mode. It means that |
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| 230 | we will have to re-write some mechanisms of this driver. |
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| 231 | |
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| 232 | |
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| 233 | @section List of Ethernet cards using the DEC chip |
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| 234 | |
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| 235 | Many Ethernet adapter cards use the Tulip chip. Here is a non exhaustive list |
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| 236 | of adapters which support this driver : |
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| 237 | |
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| 238 | @itemize @bullet |
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| 239 | @item Accton EtherDuo PCI. |
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| 240 | @item Accton EN1207 All three media types supported. |
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| 241 | @item Adaptec ANA6911/TX 21140-AC. |
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| 242 | @item Cogent EM110 21140-A with DP83840 N-Way MII transceiver. |
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| 243 | @item Cogent EM400 EM100 with 4 21140 100mbps-only ports + PCI Bridge. |
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| 244 | @item Danpex EN-9400P3. |
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| 245 | @item D-Link DFE500-Tx 21140-A with DP83840 transceiver. |
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| 246 | @item Kingston EtherX KNE100TX 21140AE. |
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| 247 | @item Netgear FX310 TX 10/100 21140AE. |
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| 248 | @item SMC EtherPower10/100 With DEC21140 and 68836 SYM transceiver. |
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| 249 | @item SMC EtherPower10/100 With DEC21140-AC and DP83840 MII transceiver. |
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| 250 | Note: The EtherPower II uses the EPIC chip, which requires a different driver. |
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| 251 | @item Surecom EP-320X DEC 21140. |
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| 252 | @item Thomas Conrad TC5048. |
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| 253 | @item Znyx ZX345 21140-A, usually with the DP83840 N-Way MII transciever. Some ZX345 |
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| 254 | cards made in 1996 have an ICS 1890 transciver instead. |
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| 255 | @item ZNYX ZX348 Two 21140-A chips using ICS 1890 transcievers and either a 21052 |
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| 256 | or 21152 bridge. Early versions used National 83840 transcievers, but later |
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| 257 | versions are depopulated ZX346 boards. |
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| 258 | @item ZNYX ZX351 21140 chip with a Broadcom 100BaseT4 transciever. |
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| 259 | @end itemize |
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| 260 | |
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| 261 | Our DEC driver has not been tested with all these cards, only with the D-Link |
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| 262 | DFE500-TX. |
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| 263 | |
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| 264 | @itemize @code{ } |
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| 265 | @item @cite{[DEC21140 Hardware Manual] DIGITAL, @b{DIGITAL |
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| 266 | Semiconductor 21140A PCI Fast Ethernet LAN Controller - Hardware |
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| 267 | Reference Manual}}. |
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| 268 | |
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| 269 | @item @cite{[99.TA.0021.M.ER]Emmanuel Raguet, |
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| 270 | @b{RTEMS Cache Management For Intel}}. |
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[936ae5d] | 271 | @end itemize |
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