1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | |
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6 | @ifinfo |
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7 | @end ifinfo |
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8 | @chapter SPARC Specific Information |
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9 | |
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10 | The Real Time Executive for Multiprocessor Systems |
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11 | (RTEMS) is designed to be portable across multiple processor |
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12 | architectures. However, the nature of real-time systems makes |
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13 | it essential that the application designer understand certain |
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14 | processor dependent implementation details. These processor |
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15 | dependencies include calling convention, board support package |
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16 | issues, interrupt processing, exact RTEMS memory requirements, |
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17 | performance data, header files, and the assembly language |
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18 | interface to the executive. |
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19 | |
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20 | This document discusses the SPARC architecture dependencies in this |
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21 | port of RTEMS. This architectural port is for SPARC Version 7 and |
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22 | 8. Implementations for SPARC V9 are in the sparc64 target. |
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23 | |
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24 | It is highly recommended that the SPARC RTEMS |
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25 | application developer obtain and become familiar with the |
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26 | documentation for the processor being used as well as the |
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27 | specification for the revision of the SPARC architecture which |
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28 | corresponds to that processor. |
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29 | |
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30 | @subheading SPARC Architecture Documents |
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31 | |
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32 | For information on the SPARC architecture, refer to |
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33 | the following documents available from SPARC International, Inc. |
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34 | (http://www.sparc.com): |
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35 | |
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36 | @itemize @bullet |
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37 | @item SPARC Standard Version 7. |
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38 | |
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39 | @item SPARC Standard Version 8. |
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40 | @end itemize |
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41 | |
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42 | @subheading ERC32 Specific Information |
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43 | |
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44 | The European Space Agency's ERC32 is a three chip |
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45 | computing core implementing a SPARC V7 processor and associated |
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46 | support circuitry for embedded space applications. The integer |
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47 | and floating-point units (90C601E & 90C602E) are based on the |
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48 | Cypress 7C601 and 7C602, with additional error-detection and |
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49 | recovery functions. The memory controller (MEC) implements |
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50 | system support functions such as address decoding, memory |
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51 | interface, DMA interface, UARTs, timers, interrupt control, |
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52 | write-protection, memory reconfiguration and error-detection. |
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53 | The core is designed to work at 25MHz, but using space qualified |
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54 | memories limits the system frequency to around 15 MHz, resulting |
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55 | in a performance of 10 MIPS and 2 MFLOPS. |
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56 | |
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57 | Information on the ERC32 and a number of development |
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58 | support tools, such as the SPARC Instruction Simulator (SIS), |
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59 | are freely available on the Internet. The following documents |
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60 | and SIS are available via anonymous ftp or pointing your web |
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61 | browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. |
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62 | |
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63 | @itemize @bullet |
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64 | @item ERC32 System Design Document |
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65 | |
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66 | @item MEC Device Specification |
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67 | @end itemize |
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68 | |
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69 | Additionally, the SPARC RISC User's Guide from Matra |
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70 | MHS documents the functionality of the integer and floating |
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71 | point units including the instruction set information. To |
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72 | obtain this document as well as ERC32 components and VHDL models |
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73 | contact: |
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74 | |
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75 | @example |
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76 | Matra MHS SA |
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77 | 3 Avenue du Centre, BP 309, |
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78 | 78054 St-Quentin-en-Yvelines, |
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79 | Cedex, France |
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80 | VOICE: +31-1-30607087 |
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81 | FAX: +31-1-30640693 |
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82 | @end example |
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83 | |
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84 | Amar Guennon (amar.guennon@@matramhs.fr) is familiar with the ERC32. |
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85 | |
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86 | @c |
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87 | @c COPYRIGHT (c) 1988-2002. |
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88 | @c On-Line Applications Research Corporation (OAR). |
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89 | @c All rights reserved. |
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90 | |
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91 | @section CPU Model Dependent Features |
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92 | |
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93 | |
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94 | Microprocessors are generally classified into |
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95 | families with a variety of CPU models or implementations within |
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96 | that family. Within a processor family, there is a high level |
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97 | of binary compatibility. This family may be based on either an |
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98 | architectural specification or on maintaining compatibility with |
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99 | a popular processor. Recent microprocessor families such as the |
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100 | SPARC or PowerPC are based on an architectural specification |
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101 | which is independent or any particular CPU model or |
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102 | implementation. Older families such as the M68xxx and the iX86 |
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103 | evolved as the manufacturer strived to produce higher |
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104 | performance processor models which maintained binary |
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105 | compatibility with older models. |
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106 | |
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107 | RTEMS takes advantage of the similarity of the |
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108 | various models within a CPU family. Although the models do vary |
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109 | in significant ways, the high level of compatibility makes it |
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110 | possible to share the bulk of the CPU dependent executive code |
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111 | across the entire family. |
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112 | |
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113 | @subsection CPU Model Feature Flags |
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114 | |
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115 | Each processor family supported by RTEMS has a |
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116 | list of features which vary between CPU models |
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117 | within a family. For example, the most common model dependent |
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118 | feature regardless of CPU family is the presence or absence of a |
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119 | floating point unit or coprocessor. When defining the list of |
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120 | features present on a particular CPU model, one simply notes |
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121 | that floating point hardware is or is not present and defines a |
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122 | single constant appropriately. Conditional compilation is |
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123 | utilized to include the appropriate source code for this CPU |
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124 | model's feature set. It is important to note that this means |
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125 | that RTEMS is thus compiled using the appropriate feature set |
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126 | and compilation flags optimal for this CPU model used. The |
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127 | alternative would be to generate a binary which would execute on |
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128 | all family members using only the features which were always |
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129 | present. |
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130 | |
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131 | This section presents the set of features which vary |
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132 | across SPARC implementations and are of importance to RTEMS. |
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133 | The set of CPU model feature macros are defined in the file |
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134 | cpukit/score/cpu/sparc/sparc.h based upon the particular CPU |
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135 | model defined on the compilation command line. |
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136 | |
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137 | @subsubsection CPU Model Name |
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138 | |
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139 | The macro CPU_MODEL_NAME is a string which designates |
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140 | the name of this CPU model. For example, for the European Space |
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141 | Agency's ERC32 SPARC model, this macro is set to the string |
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142 | "erc32". |
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143 | |
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144 | @subsubsection Floating Point Unit |
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145 | |
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146 | The macro SPARC_HAS_FPU is set to 1 to indicate that |
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147 | this CPU model has a hardware floating point unit and 0 |
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148 | otherwise. |
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149 | |
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150 | @subsubsection Bitscan Instruction |
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151 | |
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152 | The macro SPARC_HAS_BITSCAN is set to 1 to indicate |
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153 | that this CPU model has the bitscan instruction. For example, |
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154 | this instruction is supported by the Fujitsu SPARClite family. |
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155 | |
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156 | @subsubsection Number of Register Windows |
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157 | |
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158 | The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to |
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159 | indicate the number of register window sets implemented by this |
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160 | CPU model. The SPARC architecture allows a for a maximum of |
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161 | thirty-two register window sets although most implementations |
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162 | only include eight. |
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163 | |
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164 | @subsubsection Low Power Mode |
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165 | |
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166 | The macro SPARC_HAS_LOW_POWER_MODE is set to one to |
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167 | indicate that this CPU model has a low power mode. If low power |
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168 | is enabled, then there must be CPU model specific implementation |
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169 | of the IDLE task in cpukit/score/cpu/sparc/cpu.c. The low |
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170 | power mode IDLE task should be of the form: |
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171 | |
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172 | @example |
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173 | while ( TRUE ) @{ |
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174 | enter low power mode |
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175 | @} |
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176 | @end example |
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177 | |
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178 | The code required to enter low power mode is CPU model specific. |
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179 | |
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180 | @subsection CPU Model Implementation Notes |
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181 | |
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182 | The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602 |
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183 | chipset. This CPU has a number of on-board peripherals and was developed by |
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184 | the European Space Agency to target space applications. RTEMS currently |
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185 | provides support for the following peripherals: |
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186 | |
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187 | @itemize @bullet |
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188 | @item UART Channels A and B |
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189 | @item General Purpose Timer |
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190 | @item Real Time Clock |
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191 | @item Watchdog Timer (so it can be disabled) |
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192 | @item Control Register (so powerdown mode can be enabled) |
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193 | @item Memory Control Register |
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194 | @item Interrupt Control |
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195 | @end itemize |
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196 | |
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197 | The General Purpose Timer and Real Time Clock Timer provided with the ERC32 |
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198 | share the Timer Control Register. Because the Timer Control Register is write |
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199 | only, we must mirror it in software and insure that writes to one timer do not |
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200 | alter the current settings and status of the other timer. Routines are |
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201 | provided in erc32.h which promote the view that the two timers are completely |
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202 | independent. By exclusively using these routines to access the Timer Control |
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203 | Register, the application can view the system as having a General Purpose |
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204 | Timer Control Register and a Real Time Clock Timer Control Register |
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205 | rather than the single shared value. |
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206 | |
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207 | The RTEMS Idle thread take advantage of the low power mode provided by the |
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208 | ERC32. Low power mode is entered during idle loops and is enabled at |
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209 | initialization time. |
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210 | @c |
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211 | @c COPYRIGHT (c) 1988-2002. |
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212 | @c On-Line Applications Research Corporation (OAR). |
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213 | @c All rights reserved. |
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214 | |
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215 | @section Calling Conventions |
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216 | |
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217 | |
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218 | Each high-level language compiler generates |
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219 | subroutine entry and exit code based upon a set of rules known |
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220 | as the compiler's calling convention. These rules address the |
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221 | following issues: |
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222 | |
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223 | @itemize @bullet |
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224 | @item register preservation and usage |
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225 | |
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226 | @item parameter passing |
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227 | |
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228 | @item call and return mechanism |
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229 | @end itemize |
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230 | |
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231 | A compiler's calling convention is of importance when |
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232 | interfacing to subroutines written in another language either |
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233 | assembly or high-level. Even when the high-level language and |
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234 | target processor are the same, different compilers may use |
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235 | different calling conventions. As a result, calling conventions |
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236 | are both processor and compiler dependent. |
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237 | |
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238 | @subsection Programming Model |
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239 | |
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240 | This section discusses the programming model for the |
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241 | SPARC architecture. |
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242 | |
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243 | @subsubsection Non-Floating Point Registers |
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244 | |
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245 | The SPARC architecture defines thirty-two |
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246 | non-floating point registers directly visible to the programmer. |
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247 | These are divided into four sets: |
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248 | |
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249 | @itemize @bullet |
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250 | @item input registers |
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251 | |
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252 | @item local registers |
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253 | |
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254 | @item output registers |
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255 | |
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256 | @item global registers |
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257 | @end itemize |
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258 | |
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259 | Each register is referred to by either two or three |
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260 | names in the SPARC reference manuals. First, the registers are |
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261 | referred to as r0 through r31 or with the alternate notation |
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262 | r[0] through r[31]. Second, each register is a member of one of |
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263 | the four sets listed above. Finally, some registers have an |
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264 | architecturally defined role in the programming model which |
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265 | provides an alternate name. The following table describes the |
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266 | mapping between the 32 registers and the register sets: |
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267 | |
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268 | @ifset use-ascii |
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269 | @example |
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270 | @group |
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271 | +-----------------+----------------+------------------+ |
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272 | | Register Number | Register Names | Description | |
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273 | +-----------------+----------------+------------------+ |
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274 | | 0 - 7 | g0 - g7 | Global Registers | |
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275 | +-----------------+----------------+------------------+ |
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276 | | 8 - 15 | o0 - o7 | Output Registers | |
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277 | +-----------------+----------------+------------------+ |
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278 | | 16 - 23 | l0 - l7 | Local Registers | |
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279 | +-----------------+----------------+------------------+ |
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280 | | 24 - 31 | i0 - i7 | Input Registers | |
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281 | +-----------------+----------------+------------------+ |
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282 | @end group |
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283 | @end example |
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284 | @end ifset |
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285 | |
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286 | @ifset use-tex |
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287 | @sp 1 |
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288 | @tex |
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289 | \centerline{\vbox{\offinterlineskip\halign{ |
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290 | \vrule\strut#& |
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291 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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292 | \vrule#& |
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293 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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294 | \vrule#& |
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295 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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296 | \vrule#\cr |
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297 | \noalign{\hrule} |
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298 | &\bf Register Number &&\bf Register Names&&\bf Description&\cr\noalign{\hrule} |
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299 | &0 - 7&&g0 - g7&&Global Registers&\cr\noalign{\hrule} |
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300 | &8 - 15&&o0 - o7&&Output Registers&\cr\noalign{\hrule} |
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301 | &16 - 23&&l0 - l7&&Local Registers&\cr\noalign{\hrule} |
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302 | &24 - 31&&i0 - i7&&Input Registers&\cr\noalign{\hrule} |
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303 | }}\hfil} |
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304 | @end tex |
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305 | @end ifset |
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306 | |
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307 | @ifset use-html |
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308 | @html |
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309 | <CENTER> |
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310 | <TABLE COLS=3 WIDTH="80%" BORDER=2> |
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311 | <TR><TD ALIGN=center><STRONG>Register Number</STRONG></TD> |
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312 | <TD ALIGN=center><STRONG>Register Names</STRONG></TD> |
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313 | <TD ALIGN=center><STRONG>Description</STRONG></TD> |
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314 | <TR><TD ALIGN=center>0 - 7</TD> |
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315 | <TD ALIGN=center>g0 - g7</TD> |
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316 | <TD ALIGN=center>Global Registers</TD></TR> |
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317 | <TR><TD ALIGN=center>8 - 15</TD> |
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318 | <TD ALIGN=center>o0 - o7</TD> |
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319 | <TD ALIGN=center>Output Registers</TD></TR> |
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320 | <TR><TD ALIGN=center>16 - 23</TD> |
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321 | <TD ALIGN=center>l0 - l7</TD> |
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322 | <TD ALIGN=center>Local Registers</TD></TR> |
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323 | <TR><TD ALIGN=center>24 - 31</TD> |
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324 | <TD ALIGN=center>i0 - i7</TD> |
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325 | <TD ALIGN=center>Input Registers</TD></TR> |
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326 | </TABLE> |
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327 | </CENTER> |
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328 | @end html |
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329 | @end ifset |
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330 | |
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331 | As mentioned above, some of the registers serve |
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332 | defined roles in the programming model. The following table |
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333 | describes the role of each of these registers: |
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334 | |
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335 | @ifset use-ascii |
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336 | @example |
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337 | @group |
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338 | +---------------+----------------+----------------------+ |
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339 | | Register Name | Alternate Name | Description | |
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340 | +---------------+----------------+----------------------+ |
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341 | | g0 | na | reads return 0 | |
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342 | | | | writes are ignored | |
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343 | +---------------+----------------+----------------------+ |
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344 | | o6 | sp | stack pointer | |
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345 | +---------------+----------------+----------------------+ |
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346 | | i6 | fp | frame pointer | |
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347 | +---------------+----------------+----------------------+ |
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348 | | i7 | na | return address | |
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349 | +---------------+----------------+----------------------+ |
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350 | @end group |
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351 | @end example |
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352 | @end ifset |
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353 | |
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354 | @ifset use-tex |
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355 | @sp 1 |
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356 | @tex |
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357 | \centerline{\vbox{\offinterlineskip\halign{ |
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358 | \vrule\strut#& |
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359 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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360 | \vrule#& |
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361 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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362 | \vrule#& |
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363 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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364 | \vrule#\cr |
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365 | \noalign{\hrule} |
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366 | &\bf Register Name &&\bf Alternate Names&&\bf Description&\cr\noalign{\hrule} |
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367 | &g0&&NA&&reads return 0; &\cr |
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368 | &&&&&writes are ignored&\cr\noalign{\hrule} |
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369 | &o6&&sp&&stack pointer&\cr\noalign{\hrule} |
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370 | &i6&&fp&&frame pointer&\cr\noalign{\hrule} |
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371 | &i7&&NA&&return address&\cr\noalign{\hrule} |
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372 | }}\hfil} |
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373 | @end tex |
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374 | @end ifset |
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375 | |
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376 | @ifset use-html |
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377 | @html |
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378 | <CENTER> |
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379 | <TABLE COLS=3 WIDTH="80%" BORDER=2> |
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380 | <TR><TD ALIGN=center><STRONG>Register Name</STRONG></TD> |
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381 | <TD ALIGN=center><STRONG>Alternate Name</STRONG></TD> |
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382 | <TD ALIGN=center><STRONG>Description</STRONG></TD></TR> |
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383 | <TR><TD ALIGN=center>g0</TD> |
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384 | <TD ALIGN=center>NA</TD> |
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385 | <TD ALIGN=center>reads return 0 ; writes are ignored</TD></TR> |
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386 | <TR><TD ALIGN=center>o6</TD> |
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387 | <TD ALIGN=center>sp</TD> |
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388 | <TD ALIGN=center>stack pointer</TD></TR> |
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389 | <TR><TD ALIGN=center>i6</TD> |
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390 | <TD ALIGN=center>fp</TD> |
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391 | <TD ALIGN=center>frame pointer</TD></TR> |
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392 | <TR><TD ALIGN=center>i7</TD> |
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393 | <TD ALIGN=center>NA</TD> |
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394 | <TD ALIGN=center>return address</TD></TR> |
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395 | </TABLE> |
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396 | </CENTER> |
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397 | @end html |
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398 | @end ifset |
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399 | |
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400 | The registers g2 through g4 are reserved for applications. GCC uses them as |
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401 | volatile registers by default. So they are treated like volatile registers in |
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402 | RTEMS as well. |
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403 | |
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404 | The register g6 is reserved for the operating system and contains the address |
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405 | of the per-CPU control block of the current processor. This register is |
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406 | initialized during system start and then remains unchanged. It is not |
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407 | saved/restored by the context switch or interrupt processing code. |
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408 | |
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409 | The register g7 is reserved for the operating system and contains the thread |
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410 | pointer used for thread-local storage (TLS) as mandated by the SPARC ABI. |
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411 | |
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412 | @subsubsection Floating Point Registers |
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413 | |
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414 | The SPARC V7 architecture includes thirty-two, |
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415 | thirty-two bit registers. These registers may be viewed as |
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416 | follows: |
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417 | |
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418 | @itemize @bullet |
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419 | @item 32 single precision floating point or integer registers |
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420 | (f0, f1, ... f31) |
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421 | |
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422 | @item 16 double precision floating point registers (f0, f2, |
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423 | f4, ... f30) |
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424 | |
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425 | @item 8 extended precision floating point registers (f0, f4, |
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426 | f8, ... f28) |
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427 | @end itemize |
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428 | |
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429 | The floating point status register (fpsr) specifies |
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430 | the behavior of the floating point unit for rounding, contains |
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431 | its condition codes, version specification, and trap information. |
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432 | |
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433 | A queue of the floating point instructions which have |
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434 | started execution but not yet completed is maintained. This |
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435 | queue is needed to support the multiple cycle nature of floating |
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436 | point operations and to aid floating point exception trap |
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437 | handlers. Once a floating point exception has been encountered, |
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438 | the queue is frozen until it is emptied by the trap handler. |
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439 | The floating point queue is loaded by launching instructions. |
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440 | It is emptied normally when the floating point completes all |
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441 | outstanding instructions and by floating point exception |
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442 | handlers with the store double floating point queue (stdfq) |
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443 | instruction. |
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444 | |
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445 | @subsubsection Special Registers |
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446 | |
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447 | The SPARC architecture includes two special registers |
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448 | which are critical to the programming model: the Processor State |
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449 | Register (psr) and the Window Invalid Mask (wim). The psr |
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450 | contains the condition codes, processor interrupt level, trap |
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451 | enable bit, supervisor mode and previous supervisor mode bits, |
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452 | version information, floating point unit and coprocessor enable |
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453 | bits, and the current window pointer (cwp). The cwp field of |
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454 | the psr and wim register are used to manage the register windows |
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455 | in the SPARC architecture. The register windows are discussed |
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456 | in more detail below. |
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457 | |
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458 | @subsection Register Windows |
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459 | |
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460 | The SPARC architecture includes the concept of |
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461 | register windows. An overly simplistic way to think of these |
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462 | windows is to imagine them as being an infinite supply of |
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463 | "fresh" register sets available for each subroutine to use. In |
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464 | reality, they are much more complicated. |
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465 | |
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466 | The save instruction is used to obtain a new register |
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467 | window. This instruction decrements the current window pointer, |
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468 | thus providing a new set of registers for use. This register |
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469 | set includes eight fresh local registers for use exclusively by |
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470 | this subroutine. When done with a register set, the restore |
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471 | instruction increments the current window pointer and the |
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472 | previous register set is once again available. |
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473 | |
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474 | The two primary issues complicating the use of |
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475 | register windows are that (1) the set of register windows is |
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476 | finite, and (2) some registers are shared between adjacent |
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477 | registers windows. |
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478 | |
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479 | Because the set of register windows is finite, it is |
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480 | possible to execute enough save instructions without |
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481 | corresponding restore's to consume all of the register windows. |
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482 | This is easily accomplished in a high level language because |
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483 | each subroutine typically performs a save instruction upon |
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484 | entry. Thus having a subroutine call depth greater than the |
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485 | number of register windows will result in a window overflow |
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486 | condition. The window overflow condition generates a trap which |
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487 | must be handled in software. The window overflow trap handler |
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488 | is responsible for saving the contents of the oldest register |
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489 | window on the program stack. |
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490 | |
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491 | Similarly, the subroutines will eventually complete |
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492 | and begin to perform restore's. If the restore results in the |
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493 | need for a register window which has previously been written to |
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494 | memory as part of an overflow, then a window underflow condition |
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495 | results. Just like the window overflow, the window underflow |
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496 | condition must be handled in software by a trap handler. The |
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497 | window underflow trap handler is responsible for reloading the |
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498 | contents of the register window requested by the restore |
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499 | instruction from the program stack. |
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500 | |
---|
501 | The Window Invalid Mask (wim) and the Current Window |
---|
502 | Pointer (cwp) field in the psr are used in conjunction to manage |
---|
503 | the finite set of register windows and detect the window |
---|
504 | overflow and underflow conditions. The cwp contains the index |
---|
505 | of the register window currently in use. The save instruction |
---|
506 | decrements the cwp modulo the number of register windows. |
---|
507 | Similarly, the restore instruction increments the cwp modulo the |
---|
508 | number of register windows. Each bit in the wim represents |
---|
509 | represents whether a register window contains valid information. |
---|
510 | The value of 0 indicates the register window is valid and 1 |
---|
511 | indicates it is invalid. When a save instruction causes the cwp |
---|
512 | to point to a register window which is marked as invalid, a |
---|
513 | window overflow condition results. Conversely, the restore |
---|
514 | instruction may result in a window underflow condition. |
---|
515 | |
---|
516 | Other than the assumption that a register window is |
---|
517 | always available for trap (i.e. interrupt) handlers, the SPARC |
---|
518 | architecture places no limits on the number of register windows |
---|
519 | simultaneously marked as invalid (i.e. number of bits set in the |
---|
520 | wim). However, RTEMS assumes that only one register window is |
---|
521 | marked invalid at a time (i.e. only one bit set in the wim). |
---|
522 | This makes the maximum possible number of register windows |
---|
523 | available to the user while still meeting the requirement that |
---|
524 | window overflow and underflow conditions can be detected. |
---|
525 | |
---|
526 | The window overflow and window underflow trap |
---|
527 | handlers are a critical part of the run-time environment for a |
---|
528 | SPARC application. The SPARC architectural specification allows |
---|
529 | for the number of register windows to be any power of two less |
---|
530 | than or equal to 32. The most common choice for SPARC |
---|
531 | implementations appears to be 8 register windows. This results |
---|
532 | in the cwp ranging in value from 0 to 7 on most implementations. |
---|
533 | |
---|
534 | |
---|
535 | The second complicating factor is the sharing of |
---|
536 | registers between adjacent register windows. While each |
---|
537 | register window has its own set of local registers, the input |
---|
538 | and output registers are shared between adjacent windows. The |
---|
539 | output registers for register window N are the same as the input |
---|
540 | registers for register window ((N - 1) modulo RW) where RW is |
---|
541 | the number of register windows. An alternative way to think of |
---|
542 | this is to remember how parameters are passed to a subroutine on |
---|
543 | the SPARC. The caller loads values into what are its output |
---|
544 | registers. Then after the callee executes a save instruction, |
---|
545 | those parameters are available in its input registers. This is |
---|
546 | a very efficient way to pass parameters as no data is actually |
---|
547 | moved by the save or restore instructions. |
---|
548 | |
---|
549 | @subsection Call and Return Mechanism |
---|
550 | |
---|
551 | The SPARC architecture supports a simple yet |
---|
552 | effective call and return mechanism. A subroutine is invoked |
---|
553 | via the call (call) instruction. This instruction places the |
---|
554 | return address in the caller's output register 7 (o7). After |
---|
555 | the callee executes a save instruction, this value is available |
---|
556 | in input register 7 (i7) until the corresponding restore |
---|
557 | instruction is executed. |
---|
558 | |
---|
559 | The callee returns to the caller via a jmp to the |
---|
560 | return address. There is a delay slot following this |
---|
561 | instruction which is commonly used to execute a restore |
---|
562 | instruction -- if a register window was allocated by this |
---|
563 | subroutine. |
---|
564 | |
---|
565 | It is important to note that the SPARC subroutine |
---|
566 | call and return mechanism does not automatically save and |
---|
567 | restore any registers. This is accomplished via the save and |
---|
568 | restore instructions which manage the set of registers windows. |
---|
569 | |
---|
570 | @subsection Calling Mechanism |
---|
571 | |
---|
572 | All RTEMS directives are invoked using the regular |
---|
573 | SPARC calling convention via the call instruction. |
---|
574 | |
---|
575 | @subsection Register Usage |
---|
576 | |
---|
577 | As discussed above, the call instruction does not |
---|
578 | automatically save any registers. The save and restore |
---|
579 | instructions are used to allocate and deallocate register |
---|
580 | windows. When a register window is allocated, the new set of |
---|
581 | local registers are available for the exclusive use of the |
---|
582 | subroutine which allocated this register set. |
---|
583 | |
---|
584 | @subsection Parameter Passing |
---|
585 | |
---|
586 | RTEMS assumes that arguments are placed in the |
---|
587 | caller's output registers with the first argument in output |
---|
588 | register 0 (o0), the second argument in output register 1 (o1), |
---|
589 | and so forth. Until the callee executes a save instruction, the |
---|
590 | parameters are still visible in the output registers. After the |
---|
591 | callee executes a save instruction, the parameters are visible |
---|
592 | in the corresponding input registers. The following pseudo-code |
---|
593 | illustrates the typical sequence used to call a RTEMS directive |
---|
594 | with three (3) arguments: |
---|
595 | |
---|
596 | @example |
---|
597 | load third argument into o2 |
---|
598 | load second argument into o1 |
---|
599 | load first argument into o0 |
---|
600 | invoke directive |
---|
601 | @end example |
---|
602 | |
---|
603 | @subsection User-Provided Routines |
---|
604 | |
---|
605 | All user-provided routines invoked by RTEMS, such as |
---|
606 | user extensions, device drivers, and MPCI routines, must also |
---|
607 | adhere to these calling conventions. |
---|
608 | |
---|
609 | @c |
---|
610 | @c COPYRIGHT (c) 1988-2002. |
---|
611 | @c On-Line Applications Research Corporation (OAR). |
---|
612 | @c All rights reserved. |
---|
613 | |
---|
614 | @section Memory Model |
---|
615 | |
---|
616 | |
---|
617 | A processor may support any combination of memory |
---|
618 | models ranging from pure physical addressing to complex demand |
---|
619 | paged virtual memory systems. RTEMS supports a flat memory |
---|
620 | model which ranges contiguously over the processor's allowable |
---|
621 | address space. RTEMS does not support segmentation or virtual |
---|
622 | memory of any kind. The appropriate memory model for RTEMS |
---|
623 | provided by the targeted processor and related characteristics |
---|
624 | of that model are described in this chapter. |
---|
625 | |
---|
626 | @subsection Flat Memory Model |
---|
627 | |
---|
628 | The SPARC architecture supports a flat 32-bit address |
---|
629 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
---|
630 | gigabytes). Each address is represented by a 32-bit value and |
---|
631 | is byte addressable. The address may be used to reference a |
---|
632 | single byte, half-word (2-bytes), word (4 bytes), or doubleword |
---|
633 | (8 bytes). Memory accesses within this address space are |
---|
634 | performed in big endian fashion by the SPARC. Memory accesses |
---|
635 | which are not properly aligned generate a "memory address not |
---|
636 | aligned" trap (type number 7). The following table lists the |
---|
637 | alignment requirements for a variety of data accesses: |
---|
638 | |
---|
639 | @ifset use-ascii |
---|
640 | @example |
---|
641 | @group |
---|
642 | +--------------+-----------------------+ |
---|
643 | | Data Type | Alignment Requirement | |
---|
644 | +--------------+-----------------------+ |
---|
645 | | byte | 1 | |
---|
646 | | half-word | 2 | |
---|
647 | | word | 4 | |
---|
648 | | doubleword | 8 | |
---|
649 | +--------------+-----------------------+ |
---|
650 | @end group |
---|
651 | @end example |
---|
652 | @end ifset |
---|
653 | |
---|
654 | @ifset use-tex |
---|
655 | @sp 1 |
---|
656 | @tex |
---|
657 | \centerline{\vbox{\offinterlineskip\halign{ |
---|
658 | \vrule\strut#& |
---|
659 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
---|
660 | \vrule#& |
---|
661 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
---|
662 | \vrule#\cr |
---|
663 | \noalign{\hrule} |
---|
664 | &\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule} |
---|
665 | &byte&&1&\cr\noalign{\hrule} |
---|
666 | &half-word&&2&\cr\noalign{\hrule} |
---|
667 | &word&&4&\cr\noalign{\hrule} |
---|
668 | &doubleword&&8&\cr\noalign{\hrule} |
---|
669 | }}\hfil} |
---|
670 | @end tex |
---|
671 | @end ifset |
---|
672 | |
---|
673 | @ifset use-html |
---|
674 | @html |
---|
675 | <CENTER> |
---|
676 | <TABLE COLS=2 WIDTH="60%" BORDER=2> |
---|
677 | <TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD> |
---|
678 | <TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR> |
---|
679 | <TR><TD ALIGN=center>byte</TD> |
---|
680 | <TD ALIGN=center>1</TD></TR> |
---|
681 | <TR><TD ALIGN=center>half-word</TD> |
---|
682 | <TD ALIGN=center>2</TD></TR> |
---|
683 | <TR><TD ALIGN=center>word</TD> |
---|
684 | <TD ALIGN=center>4</TD></TR> |
---|
685 | <TR><TD ALIGN=center>doubleword</TD> |
---|
686 | <TD ALIGN=center>8</TD></TR> |
---|
687 | </TABLE> |
---|
688 | </CENTER> |
---|
689 | @end html |
---|
690 | @end ifset |
---|
691 | |
---|
692 | Doubleword load and store operations must use a pair |
---|
693 | of registers as their source or destination. This pair of |
---|
694 | registers must be an adjacent pair of registers with the first |
---|
695 | of the pair being even numbered. For example, a valid |
---|
696 | destination for a doubleword load might be input registers 0 and |
---|
697 | 1 (i0 and i1). The pair i1 and i2 would be invalid. [NOTE: |
---|
698 | Some assemblers for the SPARC do not generate an error if an odd |
---|
699 | numbered register is specified as the beginning register of the |
---|
700 | pair. In this case, the assembler assumes that what the |
---|
701 | programmer meant was to use the even-odd pair which ends at the |
---|
702 | specified register. This may or may not have been a correct |
---|
703 | assumption.] |
---|
704 | |
---|
705 | RTEMS does not support any SPARC Memory Management |
---|
706 | Units, therefore, virtual memory or segmentation systems |
---|
707 | involving the SPARC are not supported. |
---|
708 | |
---|
709 | @c |
---|
710 | @c COPYRIGHT (c) 1988-2002. |
---|
711 | @c On-Line Applications Research Corporation (OAR). |
---|
712 | @c All rights reserved. |
---|
713 | |
---|
714 | @section Interrupt Processing |
---|
715 | |
---|
716 | |
---|
717 | Different types of processors respond to the |
---|
718 | occurrence of an interrupt in its own unique fashion. In |
---|
719 | addition, each processor type provides a control mechanism to |
---|
720 | allow for the proper handling of an interrupt. The processor |
---|
721 | dependent response to the interrupt modifies the current |
---|
722 | execution state and results in a change in the execution stream. |
---|
723 | Most processors require that an interrupt handler utilize some |
---|
724 | special control mechanisms to return to the normal processing |
---|
725 | stream. Although RTEMS hides many of the processor dependent |
---|
726 | details of interrupt processing, it is important to understand |
---|
727 | how the RTEMS interrupt manager is mapped onto the processor's |
---|
728 | unique architecture. Discussed in this chapter are the SPARC's |
---|
729 | interrupt response and control mechanisms as they pertain to |
---|
730 | RTEMS. |
---|
731 | |
---|
732 | RTEMS and associated documentation uses the terms |
---|
733 | interrupt and vector. In the SPARC architecture, these terms |
---|
734 | correspond to traps and trap type, respectively. The terms will |
---|
735 | be used interchangeably in this manual. |
---|
736 | |
---|
737 | @subsection Synchronous Versus Asynchronous Traps |
---|
738 | |
---|
739 | The SPARC architecture includes two classes of traps: |
---|
740 | synchronous and asynchronous. Asynchronous traps occur when an |
---|
741 | external event interrupts the processor. These traps are not |
---|
742 | associated with any instruction executed by the processor and |
---|
743 | logically occur between instructions. The instruction currently |
---|
744 | in the execute stage of the processor is allowed to complete |
---|
745 | although subsequent instructions are annulled. The return |
---|
746 | address reported by the processor for asynchronous traps is the |
---|
747 | pair of instructions following the current instruction. |
---|
748 | |
---|
749 | Synchronous traps are caused by the actions of an |
---|
750 | instruction. The trap stimulus in this case either occurs |
---|
751 | internally to the processor or is from an external signal that |
---|
752 | was provoked by the instruction. These traps are taken |
---|
753 | immediately and the instruction that caused the trap is aborted |
---|
754 | before any state changes occur in the processor itself. The |
---|
755 | return address reported by the processor for synchronous traps |
---|
756 | is the instruction which caused the trap and the following |
---|
757 | instruction. |
---|
758 | |
---|
759 | @subsection Vectoring of Interrupt Handler |
---|
760 | |
---|
761 | Upon receipt of an interrupt the SPARC automatically |
---|
762 | performs the following actions: |
---|
763 | |
---|
764 | @itemize @bullet |
---|
765 | @item disables traps (sets the ET bit of the psr to 0), |
---|
766 | |
---|
767 | @item the S bit of the psr is copied into the Previous |
---|
768 | Supervisor Mode (PS) bit of the psr, |
---|
769 | |
---|
770 | @item the cwp is decremented by one (modulo the number of |
---|
771 | register windows) to activate a trap window, |
---|
772 | |
---|
773 | @item the PC and nPC are loaded into local register 1 and 2 |
---|
774 | (l0 and l1), |
---|
775 | |
---|
776 | @item the trap type (tt) field of the Trap Base Register (TBR) |
---|
777 | is set to the appropriate value, and |
---|
778 | |
---|
779 | @item if the trap is not a reset, then the PC is written with |
---|
780 | the contents of the TBR and the nPC is written with TBR + 4. If |
---|
781 | the trap is a reset, then the PC is set to zero and the nPC is |
---|
782 | set to 4. |
---|
783 | @end itemize |
---|
784 | |
---|
785 | Trap processing on the SPARC has two features which |
---|
786 | are noticeably different than interrupt processing on other |
---|
787 | architectures. First, the value of psr register in effect |
---|
788 | immediately before the trap occurred is not explicitly saved. |
---|
789 | Instead only reversible alterations are made to it. Second, the |
---|
790 | Processor Interrupt Level (pil) is not set to correspond to that |
---|
791 | of the interrupt being processed. When a trap occurs, ALL |
---|
792 | subsequent traps are disabled. In order to safely invoke a |
---|
793 | subroutine during trap handling, traps must be enabled to allow |
---|
794 | for the possibility of register window overflow and underflow |
---|
795 | traps. |
---|
796 | |
---|
797 | If the interrupt handler was installed as an RTEMS |
---|
798 | interrupt handler, then upon receipt of the interrupt, the |
---|
799 | processor passes control to the RTEMS interrupt handler which |
---|
800 | performs the following actions: |
---|
801 | |
---|
802 | @itemize @bullet |
---|
803 | @item saves the state of the interrupted task on it's stack, |
---|
804 | |
---|
805 | @item insures that a register window is available for |
---|
806 | subsequent traps, |
---|
807 | |
---|
808 | @item if this is the outermost (i.e. non-nested) interrupt, |
---|
809 | then the RTEMS interrupt handler switches from the current stack |
---|
810 | to the interrupt stack, |
---|
811 | |
---|
812 | @item enables traps, |
---|
813 | |
---|
814 | @item invokes the vectors to a user interrupt service routine (ISR). |
---|
815 | @end itemize |
---|
816 | |
---|
817 | Asynchronous interrupts are ignored while traps are |
---|
818 | disabled. Synchronous traps which occur while traps are |
---|
819 | disabled result in the CPU being forced into an error mode. |
---|
820 | |
---|
821 | A nested interrupt is processed similarly with the |
---|
822 | exception that the current stack need not be switched to the |
---|
823 | interrupt stack. |
---|
824 | |
---|
825 | @subsection Traps and Register Windows |
---|
826 | |
---|
827 | One of the register windows must be reserved at all |
---|
828 | times for trap processing. This is critical to the proper |
---|
829 | operation of the trap mechanism in the SPARC architecture. It |
---|
830 | is the responsibility of the trap handler to insure that there |
---|
831 | is a register window available for a subsequent trap before |
---|
832 | re-enabling traps. It is likely that any high level language |
---|
833 | routines invoked by the trap handler (such as a user-provided |
---|
834 | RTEMS interrupt handler) will allocate a new register window. |
---|
835 | The save operation could result in a window overflow trap. This |
---|
836 | trap cannot be correctly processed unless (1) traps are enabled |
---|
837 | and (2) a register window is reserved for traps. Thus, the |
---|
838 | RTEMS interrupt handler insures that a register window is |
---|
839 | available for subsequent traps before enabling traps and |
---|
840 | invoking the user's interrupt handler. |
---|
841 | |
---|
842 | @subsection Interrupt Levels |
---|
843 | |
---|
844 | Sixteen levels (0-15) of interrupt priorities are |
---|
845 | supported by the SPARC architecture with level fifteen (15) |
---|
846 | being the highest priority. Level zero (0) indicates that |
---|
847 | interrupts are fully enabled. Interrupt requests for interrupts |
---|
848 | with priorities less than or equal to the current interrupt mask |
---|
849 | level are ignored. |
---|
850 | |
---|
851 | Although RTEMS supports 256 interrupt levels, the |
---|
852 | SPARC only supports sixteen. RTEMS interrupt levels 0 through |
---|
853 | 15 directly correspond to SPARC processor interrupt levels. All |
---|
854 | other RTEMS interrupt levels are undefined and their behavior is |
---|
855 | unpredictable. |
---|
856 | |
---|
857 | @subsection Disabling of Interrupts by RTEMS |
---|
858 | |
---|
859 | During the execution of directive calls, critical |
---|
860 | sections of code may be executed. When these sections are |
---|
861 | encountered, RTEMS disables interrupts to level seven (15) |
---|
862 | before the execution of this section and restores them to the |
---|
863 | previous level upon completion of the section. RTEMS has been |
---|
864 | optimized to insure that interrupts are disabled for less than |
---|
865 | RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ |
---|
866 | Mhz ERC32 with zero wait states. |
---|
867 | These numbers will vary based the number of wait states and |
---|
868 | processor speed present on the target board. |
---|
869 | [NOTE: The maximum period with interrupts disabled is hand calculated. This |
---|
870 | calculation was last performed for Release |
---|
871 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
---|
872 | |
---|
873 | [NOTE: It is thought that the length of time at which |
---|
874 | the processor interrupt level is elevated to fifteen by RTEMS is |
---|
875 | not anywhere near as long as the length of time ALL traps are |
---|
876 | disabled as part of the "flush all register windows" operation.] |
---|
877 | |
---|
878 | Non-maskable interrupts (NMI) cannot be disabled, and |
---|
879 | ISRs which execute at this level MUST NEVER issue RTEMS system |
---|
880 | calls. If a directive is invoked, unpredictable results may |
---|
881 | occur due to the inability of RTEMS to protect its critical |
---|
882 | sections. However, ISRs that make no system calls may safely |
---|
883 | execute as non-maskable interrupts. |
---|
884 | |
---|
885 | @subsection Interrupt Stack |
---|
886 | |
---|
887 | The SPARC architecture does not provide for a |
---|
888 | dedicated interrupt stack. Thus by default, trap handlers would |
---|
889 | execute on the stack of the RTEMS task which they interrupted. |
---|
890 | This artificially inflates the stack requirements for each task |
---|
891 | since EVERY task stack would have to include enough space to |
---|
892 | account for the worst case interrupt stack requirements in |
---|
893 | addition to it's own worst case usage. RTEMS addresses this |
---|
894 | problem on the SPARC by providing a dedicated interrupt stack |
---|
895 | managed by software. |
---|
896 | |
---|
897 | During system initialization, RTEMS allocates the |
---|
898 | interrupt stack from the Workspace Area. The amount of memory |
---|
899 | allocated for the interrupt stack is determined by the |
---|
900 | interrupt_stack_size field in the CPU Configuration Table. As |
---|
901 | part of processing a non-nested interrupt, RTEMS will switch to |
---|
902 | the interrupt stack before invoking the installed handler. |
---|
903 | |
---|
904 | @c |
---|
905 | @c COPYRIGHT (c) 1988-2002. |
---|
906 | @c On-Line Applications Research Corporation (OAR). |
---|
907 | @c All rights reserved. |
---|
908 | |
---|
909 | @section Default Fatal Error Processing |
---|
910 | |
---|
911 | |
---|
912 | Upon detection of a fatal error by either the |
---|
913 | application or RTEMS the fatal error manager is invoked. The |
---|
914 | fatal error manager will invoke the user-supplied fatal error |
---|
915 | handlers. If no user-supplied handlers are configured, the |
---|
916 | RTEMS provided default fatal error handler is invoked. If the |
---|
917 | user-supplied fatal error handlers return to the executive the |
---|
918 | default fatal error handler is then invoked. This chapter |
---|
919 | describes the precise operations of the default fatal error |
---|
920 | handler. |
---|
921 | |
---|
922 | @subsection Default Fatal Error Handler Operations |
---|
923 | |
---|
924 | The default fatal error handler which is invoked by |
---|
925 | the fatal_error_occurred directive when there is no user handler |
---|
926 | configured or the user handler returns control to RTEMS. The |
---|
927 | default fatal error handler disables processor interrupts to |
---|
928 | level 15, places the error code in g1, and goes into an infinite |
---|
929 | loop to simulate a halt processor instruction. |
---|
930 | |
---|
931 | @section Thread-Local Storage |
---|
932 | |
---|
933 | Thread-local storage is supported. |
---|
934 | |
---|
935 | @c |
---|
936 | @c COPYRIGHT (c) 1988-2002. |
---|
937 | @c On-Line Applications Research Corporation (OAR). |
---|
938 | @c All rights reserved. |
---|
939 | |
---|
940 | @section Board Support Packages |
---|
941 | |
---|
942 | |
---|
943 | An RTEMS Board Support Package (BSP) must be designed |
---|
944 | to support a particular processor and target board combination. |
---|
945 | This chapter presents a discussion of SPARC specific BSP issues. |
---|
946 | For more information on developing a BSP, refer to the chapter |
---|
947 | titled Board Support Packages in the RTEMS |
---|
948 | Applications User's Guide. |
---|
949 | |
---|
950 | @subsection System Reset |
---|
951 | |
---|
952 | An RTEMS based application is initiated or |
---|
953 | re-initiated when the SPARC processor is reset. When the SPARC |
---|
954 | is reset, the processor performs the following actions: |
---|
955 | |
---|
956 | @itemize @bullet |
---|
957 | @item the enable trap (ET) of the psr is set to 0 to disable |
---|
958 | traps, |
---|
959 | |
---|
960 | @item the supervisor bit (S) of the psr is set to 1 to enter |
---|
961 | supervisor mode, and |
---|
962 | |
---|
963 | @item the PC is set 0 and the nPC is set to 4. |
---|
964 | @end itemize |
---|
965 | |
---|
966 | The processor then begins to execute the code at |
---|
967 | location 0. It is important to note that all fields in the psr |
---|
968 | are not explicitly set by the above steps and all other |
---|
969 | registers retain their value from the previous execution mode. |
---|
970 | This is true even of the Trap Base Register (TBR) whose contents |
---|
971 | reflect the last trap which occurred before the reset. |
---|
972 | |
---|
973 | @subsection Processor Initialization |
---|
974 | |
---|
975 | It is the responsibility of the application's |
---|
976 | initialization code to initialize the TBR and install trap |
---|
977 | handlers for at least the register window overflow and register |
---|
978 | window underflow conditions. Traps should be enabled before |
---|
979 | invoking any subroutines to allow for register window |
---|
980 | management. However, interrupts should be disabled by setting |
---|
981 | the Processor Interrupt Level (pil) field of the psr to 15. |
---|
982 | RTEMS installs it's own Trap Table as part of initialization |
---|
983 | which is initialized with the contents of the Trap Table in |
---|
984 | place when the @code{rtems_initialize_executive} directive was invoked. |
---|
985 | Upon completion of executive initialization, interrupts are |
---|
986 | enabled. |
---|
987 | |
---|
988 | If this SPARC implementation supports on-chip caching |
---|
989 | and this is to be utilized, then it should be enabled during the |
---|
990 | reset application initialization code. |
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991 | |
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992 | In addition to the requirements described in the |
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993 | Board Support Packages chapter of the C |
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994 | Applications Users Manual for the reset code |
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995 | which is executed before the call to |
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996 | @code{rtems_initialize_executive}, the SPARC version has the following |
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997 | specific requirements: |
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998 | |
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999 | @itemize @bullet |
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1000 | @item Must leave the S bit of the status register set so that |
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1001 | the SPARC remains in the supervisor state. |
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1002 | |
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1003 | @item Must set stack pointer (sp) such that a minimum stack |
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1004 | size of MINIMUM_STACK_SIZE bytes is provided for the |
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1005 | @code{rtems_initialize_executive} directive. |
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1006 | |
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1007 | @item Must disable all external interrupts (i.e. set the pil |
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1008 | to 15). |
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1009 | |
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1010 | @item Must enable traps so window overflow and underflow |
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1011 | conditions can be properly handled. |
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1012 | |
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1013 | @item Must initialize the SPARC's initial trap table with at |
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1014 | least trap handlers for register window overflow and register |
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1015 | window underflow. |
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1016 | @end itemize |
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