1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | |
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6 | @ifinfo |
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7 | @end ifinfo |
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8 | @chapter SuperH Specific Information |
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9 | |
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10 | This chapter discusses the SuperH architecture dependencies |
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11 | in this port of RTEMS. The SuperH family has a wide variety |
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12 | of implementations by a wide range of vendors. Consequently, |
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13 | there are many, many CPU models within it. |
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14 | |
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15 | |
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16 | @subheading Architecture Documents |
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17 | |
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18 | For information on the SuperH architecture, |
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19 | refer to the following documents available from VENDOR |
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20 | (@file{http//www.XXX.com/}): |
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21 | |
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22 | @itemize @bullet |
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23 | @item @cite{SuperH Family Reference, VENDOR, PART NUMBER}. |
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24 | @end itemize |
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25 | |
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26 | @c |
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27 | @c |
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28 | @c |
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29 | @section CPU Model Dependent Features |
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30 | |
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31 | This chapter presents the set of features which vary |
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32 | across SuperH implementations and are of importance to RTEMS. |
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33 | The set of CPU model feature macros are defined in the file |
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34 | @code{cpukit/score/cpu/sh/sh.h} based upon the particular CPU |
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35 | model specified on the compilation command line. |
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36 | |
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37 | @subsection Another Optional Feature |
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38 | |
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39 | The macro XXX |
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40 | |
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41 | @c |
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42 | @c |
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43 | @c |
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44 | |
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45 | @section Calling Conventions |
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46 | |
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47 | |
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48 | @subsection Calling Mechanism |
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49 | |
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50 | All RTEMS directives are invoked using a @code{XXX} |
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51 | instruction and return to the user application via the |
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52 | @code{XXX} instruction. |
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53 | |
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54 | @subsection Register Usage |
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55 | |
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56 | The SH1 has 16 general registers (r0..r15). |
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57 | |
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58 | @itemize @bullet |
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59 | |
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60 | @item r0..r3 used as general volatile registers |
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61 | |
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62 | @item r4..r7 used to pass up to 4 arguments to functions, arguments |
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63 | above 4 are |
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64 | passed via the stack) |
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65 | |
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66 | @item r8..13 caller saved registers (i.e. push them to the stack if you |
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67 | need them inside of a function) |
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68 | |
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69 | @item r14 frame pointer |
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70 | |
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71 | @item r15 stack pointer |
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72 | |
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73 | @end itemize |
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74 | |
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75 | @subsection Parameter Passing |
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76 | |
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77 | XXX |
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78 | |
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79 | @c |
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80 | @c |
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81 | @c |
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82 | |
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83 | @section Memory Model |
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84 | |
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85 | @subsection Flat Memory Model |
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86 | |
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87 | The SuperH family supports a flat 32-bit address |
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88 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
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89 | gigabytes). Each address is represented by a 32-bit value and |
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90 | is byte addressable. The address may be used to reference a |
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91 | single byte, word (2-bytes), or long word (4 bytes). Memory |
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92 | accesses within this address space are performed in big endian |
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93 | fashion by the processors in this family. |
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94 | |
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95 | Some of the SuperH family members support virtual memory and |
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96 | segmentation. RTEMS does not support virtual memory or |
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97 | segmentation on any of the SuperH family members. It is the |
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98 | responsibility of the BSP to initialize the mapping for |
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99 | a flat memory model. |
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100 | |
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101 | @c |
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102 | @c |
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103 | @c |
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104 | |
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105 | @section Interrupt Processing |
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106 | |
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107 | Although RTEMS hides many of the processor dependent |
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108 | details of interrupt processing, it is important to understand |
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109 | how the RTEMS interrupt manager is mapped onto the processor's |
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110 | unique architecture. Discussed in this chapter are the MIPS's |
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111 | interrupt response and control mechanisms as they pertain to |
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112 | RTEMS. |
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113 | |
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114 | @subsection Vectoring of an Interrupt Handler |
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115 | |
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116 | Upon receipt of an interrupt the XXX family |
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117 | members with separate interrupt stacks automatically perform the |
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118 | following actions: |
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119 | |
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120 | @itemize @bullet |
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121 | @item TBD |
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122 | |
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123 | @end itemize |
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124 | |
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125 | A nested interrupt is processed similarly by these |
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126 | CPU models with the exception that only a single ISF is placed |
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127 | on the interrupt stack and the current stack need not be |
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128 | switched. |
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129 | |
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130 | @subsection Interrupt Levels |
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131 | |
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132 | TBD |
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133 | |
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134 | @c |
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135 | @c |
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136 | @section Default Fatal Error Processing |
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137 | |
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138 | The default fatal error handler for this architecture disables processor |
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139 | interrupts, places the error code in @b{XXX}, and executes a @code{XXX} |
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140 | instruction to simulate a halt processor instruction. |
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141 | |
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142 | @section Symmetric Multiprocessing |
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143 | |
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144 | SMP is not supported. |
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145 | |
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146 | @section Thread-Local Storage |
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147 | |
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148 | Thread-local storage is not implemented. |
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149 | |
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150 | @c |
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151 | @c |
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152 | @c |
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153 | |
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154 | @section Board Support Packages |
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155 | |
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156 | @subsection System Reset |
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157 | |
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158 | An RTEMS based application is initiated or |
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159 | re-initiated when the processor is reset. When the |
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160 | processor is reset, it performs the following actions: |
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161 | |
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162 | @itemize @bullet |
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163 | @item TBD |
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164 | |
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165 | @end itemize |
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166 | |
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167 | @subsection Processor Initialization |
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168 | |
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169 | TBD |
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