1 | @c |
---|
2 | @c COPYRIGHT (c) 1989-2007. |
---|
3 | @c On-Line Applications Research Corporation (OAR). |
---|
4 | @c All rights reserved. |
---|
5 | |
---|
6 | @ifinfo |
---|
7 | @end ifinfo |
---|
8 | @chapter PowerPC Specific Information |
---|
9 | |
---|
10 | This chapter discusses the PowerPC architecture dependencies |
---|
11 | in this port of RTEMS. The PowerPC family has a wide variety |
---|
12 | of implementations by a range of vendors. Consequently, |
---|
13 | there are many, many CPU models within it. |
---|
14 | |
---|
15 | It is highly recommended that the PowerPC RTEMS |
---|
16 | application developer obtain and become familiar with the |
---|
17 | documentation for the processor being used as well as the |
---|
18 | specification for the revision of the PowerPC architecture which |
---|
19 | corresponds to that processor. |
---|
20 | |
---|
21 | @subheading PowerPC Architecture Documents |
---|
22 | |
---|
23 | For information on the PowerPC architecture, refer to |
---|
24 | the following documents available from Motorola and IBM: |
---|
25 | |
---|
26 | @itemize @bullet |
---|
27 | |
---|
28 | @item @cite{PowerPC Microprocessor Family: The Programming Environment} |
---|
29 | (Motorola Document MPRPPCFPE-01). |
---|
30 | |
---|
31 | @item @cite{IBM PPC403GB Embedded Controller User's Manual}. |
---|
32 | |
---|
33 | @item @cite{PoweRisControl MPC500 Family RCPU RISC Central Processing |
---|
34 | Unit Reference Manual} (Motorola Document RCPUURM/AD). |
---|
35 | |
---|
36 | @item @cite{PowerPC 601 RISC Microprocessor User's Manual} |
---|
37 | (Motorola Document MPR601UM/AD). |
---|
38 | |
---|
39 | @item @cite{PowerPC 603 RISC Microprocessor User's Manual} |
---|
40 | (Motorola Document MPR603UM/AD). |
---|
41 | |
---|
42 | @item @cite{PowerPC 603e RISC Microprocessor User's Manual} |
---|
43 | (Motorola Document MPR603EUM/AD). |
---|
44 | |
---|
45 | @item @cite{PowerPC 604 RISC Microprocessor User's Manual} |
---|
46 | (Motorola Document MPR604UM/AD). |
---|
47 | |
---|
48 | @item @cite{PowerPC MPC821 Portable Systems Microprocessor User's Manual} |
---|
49 | (Motorola Document MPC821UM/AD). |
---|
50 | |
---|
51 | @item @cite{PowerQUICC MPC860 User's Manual} (Motorola Document MPC860UM/AD). |
---|
52 | |
---|
53 | @end itemize |
---|
54 | |
---|
55 | Motorola maintains an on-line electronic library for the PowerPC |
---|
56 | at the following URL: |
---|
57 | |
---|
58 | @itemize @code{ } |
---|
59 | @item @cite{http://www.mot.com/powerpc/library/library.html} |
---|
60 | @end itemize |
---|
61 | |
---|
62 | This site has a a wealth of information and examples. Many of the |
---|
63 | manuals are available from that site in electronic format. |
---|
64 | |
---|
65 | @subheading PowerPC Processor Simulator Information |
---|
66 | |
---|
67 | PSIM is a program which emulates the Instruction Set Architecture |
---|
68 | of the PowerPC microprocessor family. It is reely available in source |
---|
69 | code form under the terms of the GNU General Public License (version |
---|
70 | 2 or later). PSIM can be integrated with the GNU Debugger (gdb) to |
---|
71 | execute and debug PowerPC executables on non-PowerPC hosts. PSIM |
---|
72 | supports the addition of user provided device models which can be |
---|
73 | used to allow one to develop and debug embedded applications using |
---|
74 | the simulator. |
---|
75 | |
---|
76 | The latest version of PSIM is included in GDB and enabled on pre-built |
---|
77 | binaries provided by the RTEMS Project. |
---|
78 | |
---|
79 | @c |
---|
80 | @c |
---|
81 | @c |
---|
82 | @section CPU Model Dependent Features |
---|
83 | |
---|
84 | This section presents the set of features which vary |
---|
85 | across PowerPC implementations and are of importance to RTEMS. |
---|
86 | The set of CPU model feature macros are defined in the file |
---|
87 | @code{cpukit/score/cpu/powerpc/powerpc.h} based upon the particular CPU |
---|
88 | model specified on the compilation command line. |
---|
89 | |
---|
90 | @subsection Alignment |
---|
91 | |
---|
92 | The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment |
---|
93 | requirement for data types on a byte boundary. This value is used |
---|
94 | to derive the alignment restrictions for memory allocated from |
---|
95 | regions and partitions. |
---|
96 | |
---|
97 | @subsection Cache Alignment |
---|
98 | |
---|
99 | The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is |
---|
100 | used to align the entry point of critical routines so that as much code |
---|
101 | as possible can be retrieved with the initial read into cache. This |
---|
102 | is done for the interrupt handler as well as the context switch routines. |
---|
103 | |
---|
104 | In addition, the "shortcut" data structure used by the PowerPC implementation |
---|
105 | to ease access to data elements frequently accessed by RTEMS routines |
---|
106 | implemented in assembly language is aligned using this value. |
---|
107 | |
---|
108 | @subsection Maximum Interrupts |
---|
109 | |
---|
110 | The macro PPC_INTERRUPT_MAX is set to the number of exception sources |
---|
111 | supported by this PowerPC model. |
---|
112 | |
---|
113 | @subsection Has Double Precision Floating Point |
---|
114 | |
---|
115 | The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model |
---|
116 | has support for double precision floating point numbers. This is |
---|
117 | important because the floating point registers need only be four bytes |
---|
118 | wide (not eight) if double precision is not supported. |
---|
119 | |
---|
120 | @subsection Critical Interrupts |
---|
121 | |
---|
122 | The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model |
---|
123 | has the Critical Interrupt capability as defined by the IBM 403 models. |
---|
124 | |
---|
125 | @subsection Use Multiword Load/Store Instructions |
---|
126 | |
---|
127 | The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and |
---|
128 | store instructions should be used to perform context switch operations. |
---|
129 | The relative efficiency of multiword load and store instructions versus |
---|
130 | an equivalent set of single word load and store instructions varies based |
---|
131 | upon the PowerPC model. |
---|
132 | |
---|
133 | @subsection Instruction Cache Size |
---|
134 | |
---|
135 | The macro PPC_I_CACHE is set to the size in bytes of the instruction cache. |
---|
136 | |
---|
137 | @subsection Data Cache Size |
---|
138 | |
---|
139 | The macro PPC_D_CACHE is set to the size in bytes of the data cache. |
---|
140 | |
---|
141 | @subsection Debug Model |
---|
142 | |
---|
143 | The macro PPC_DEBUG_MODEL is set to indicate the debug support features |
---|
144 | present in this CPU model. The following debug support feature sets |
---|
145 | are currently supported: |
---|
146 | |
---|
147 | @table @b |
---|
148 | |
---|
149 | @item @code{PPC_DEBUG_MODEL_STANDARD} |
---|
150 | indicates that the single-step trace enable (SE) and branch trace |
---|
151 | enable (BE) bits in the MSR are supported by this CPU model. |
---|
152 | |
---|
153 | @item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY} |
---|
154 | indicates that only the single-step trace enable (SE) bit in the MSR |
---|
155 | is supported by this CPU model. |
---|
156 | |
---|
157 | @item @code{PPC_DEBUG_MODEL_IBM4xx} |
---|
158 | indicates that the debug exception enable (DE) bit in the MSR is supported |
---|
159 | by this CPU model. At this time, this particular debug feature set |
---|
160 | has only been seen in the IBM 4xx series. |
---|
161 | |
---|
162 | @end table |
---|
163 | |
---|
164 | @subsubsection Low Power Model |
---|
165 | |
---|
166 | The macro PPC_LOW_POWER_MODE is set to indicate the low power model |
---|
167 | supported by this CPU model. The following low power modes are currently |
---|
168 | supported. |
---|
169 | |
---|
170 | @table @b |
---|
171 | |
---|
172 | @item @code{PPC_LOW_POWER_MODE_NONE} |
---|
173 | indicates that this CPU model has no low power mode support. |
---|
174 | |
---|
175 | @item @code{PPC_LOW_POWER_MODE_STANDARD} |
---|
176 | indicates that this CPU model follows the low power model defined for |
---|
177 | the PPC603e. |
---|
178 | |
---|
179 | @end table |
---|
180 | |
---|
181 | @c |
---|
182 | @c |
---|
183 | @c |
---|
184 | |
---|
185 | @section Calling Conventions |
---|
186 | |
---|
187 | RTEMS supports the Embedded Application Binary Interface (EABI) |
---|
188 | calling convention. Documentation for EABI is available by sending |
---|
189 | a message with a subject line of "EABI" to eabi@@goth.sis.mot.com. |
---|
190 | |
---|
191 | @subsection Programming Model |
---|
192 | |
---|
193 | This section discusses the programming model for the |
---|
194 | PowerPC architecture. |
---|
195 | |
---|
196 | @subsubsection Non-Floating Point Registers |
---|
197 | |
---|
198 | The PowerPC architecture defines thirty-two non-floating point registers |
---|
199 | directly visible to the programmer. In thirty-two bit implementations, each |
---|
200 | register is thirty-two bits wide. In sixty-four bit implementations, each |
---|
201 | register is sixty-four bits wide. |
---|
202 | |
---|
203 | These registers are referred to as @code{gpr0} to @code{gpr31}. |
---|
204 | |
---|
205 | Some of the registers serve defined roles in the EABI programming model. |
---|
206 | The following table describes the role of each of these registers: |
---|
207 | |
---|
208 | @ifset use-ascii |
---|
209 | @example |
---|
210 | @group |
---|
211 | +---------------+----------------+------------------------------+ |
---|
212 | | Register Name | Alternate Name | Description | |
---|
213 | +---------------+----------------+------------------------------+ |
---|
214 | | r1 | sp | stack pointer | |
---|
215 | +---------------+----------------+------------------------------+ |
---|
216 | | | | global pointer to the Small | |
---|
217 | | r2 | na | Constant Area (SDA2) | |
---|
218 | +---------------+----------------+------------------------------+ |
---|
219 | | r3 - r12 | na | parameter and result passing | |
---|
220 | +---------------+----------------+------------------------------+ |
---|
221 | | | | global pointer to the Small | |
---|
222 | | r13 | na | Data Area (SDA) | |
---|
223 | +---------------+----------------+------------------------------+ |
---|
224 | @end group |
---|
225 | @end example |
---|
226 | @end ifset |
---|
227 | |
---|
228 | @ifset use-tex |
---|
229 | @sp 1 |
---|
230 | @tex |
---|
231 | \centerline{\vbox{\offinterlineskip\halign{ |
---|
232 | \vrule\strut#& |
---|
233 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
---|
234 | \vrule#& |
---|
235 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
---|
236 | \vrule#& |
---|
237 | \hbox to 2.50in{\enskip\hfil#\hfil}& |
---|
238 | \vrule#\cr |
---|
239 | \noalign{\hrule} |
---|
240 | &\bf Register Name &&\bf Alternate Names&&\bf Description&\cr\noalign{\hrule} |
---|
241 | &r1&&sp&&stack pointer&\cr\noalign{\hrule} |
---|
242 | &r2&&NA&&global pointer to the Small&\cr |
---|
243 | &&&&&Constant Area (SDA2)&\cr\noalign{\hrule} |
---|
244 | &r3 - r12&&NA&¶meter and result passing&\cr\noalign{\hrule} |
---|
245 | &r13&&NA&&global pointer to the Small&\cr |
---|
246 | &&&&&Data Area (SDA2)&\cr\noalign{\hrule} |
---|
247 | }}\hfil} |
---|
248 | @end tex |
---|
249 | @end ifset |
---|
250 | |
---|
251 | @ifset use-html |
---|
252 | @html |
---|
253 | <CENTER> |
---|
254 | <TABLE COLS=3 WIDTH="80%" BORDER=2> |
---|
255 | <TR><TD ALIGN=center><STRONG>Register Name</STRONG></TD> |
---|
256 | <TD ALIGN=center><STRONG>Alternate Name</STRONG></TD> |
---|
257 | <TD ALIGN=center><STRONG>Description</STRONG></TD></TR> |
---|
258 | <TR><TD ALIGN=center>r1</TD> |
---|
259 | <TD ALIGN=center>sp</TD> |
---|
260 | <TD ALIGN=center>stack pointer</TD></TR> |
---|
261 | <TR><TD ALIGN=center>r2</TD> |
---|
262 | <TD ALIGN=center>na</TD> |
---|
263 | <TD ALIGN=center>global pointer to the Small Constant Area (SDA2)</TD></TR> |
---|
264 | <TR><TD ALIGN=center>r3 - r12</TD> |
---|
265 | <TD ALIGN=center>NA</TD> |
---|
266 | <TD ALIGN=center>parameter and result passing</TD></TR> |
---|
267 | <TR><TD ALIGN=center>r13</TD> |
---|
268 | <TD ALIGN=center>NA</TD> |
---|
269 | <TD ALIGN=center>global pointer to the Small Data Area (SDA)</TD></TR> |
---|
270 | </TABLE> |
---|
271 | </CENTER> |
---|
272 | @end html |
---|
273 | @end ifset |
---|
274 | |
---|
275 | |
---|
276 | @subsubsection Floating Point Registers |
---|
277 | |
---|
278 | The PowerPC architecture includes thirty-two, sixty-four bit |
---|
279 | floating point registers. All PowerPC floating point instructions |
---|
280 | interpret these registers as 32 double precision floating point registers, |
---|
281 | regardless of whether the processor has 64-bit or 32-bit implementation. |
---|
282 | |
---|
283 | The floating point status and control register (fpscr) records exceptions |
---|
284 | and the type of result generated by floating-point operations. |
---|
285 | Additionally, it controls the rounding mode of operations and allows the |
---|
286 | reporting of floating exceptions to be enabled or disabled. |
---|
287 | |
---|
288 | @subsubsection Special Registers |
---|
289 | |
---|
290 | The PowerPC architecture includes a number of special registers |
---|
291 | which are critical to the programming model: |
---|
292 | |
---|
293 | @table @b |
---|
294 | |
---|
295 | @item Machine State Register |
---|
296 | |
---|
297 | The MSR contains the processor mode, power management mode, endian mode, |
---|
298 | exception information, privilege level, floating point available and |
---|
299 | floating point excepiton mode, address translation information and |
---|
300 | the exception prefix. |
---|
301 | |
---|
302 | @item Link Register |
---|
303 | |
---|
304 | The LR contains the return address after a function call. This register |
---|
305 | must be saved before a subsequent subroutine call can be made. The |
---|
306 | use of this register is discussed further in the @b{Call and Return |
---|
307 | Mechanism} section below. |
---|
308 | |
---|
309 | @item Count Register |
---|
310 | |
---|
311 | The CTR contains the iteration variable for some loops. It may also be used |
---|
312 | for indirect function calls and jumps. |
---|
313 | |
---|
314 | @end table |
---|
315 | |
---|
316 | @subsection Call and Return Mechanism |
---|
317 | |
---|
318 | The PowerPC architecture supports a simple yet effective call |
---|
319 | and return mechanism. A subroutine is invoked |
---|
320 | via the "branch and link" (@code{bl}) and |
---|
321 | "brank and link absolute" (@code{bla}) |
---|
322 | instructions. This instructions place the return address |
---|
323 | in the Link Register (LR). The callee returns to the caller by |
---|
324 | executing a "branch unconditional to the link register" (@code{blr}) |
---|
325 | instruction. Thus the callee returns to the caller via a jump |
---|
326 | to the return address which is stored in the LR. |
---|
327 | |
---|
328 | The previous contents of the LR are not automatically saved |
---|
329 | by either the @code{bl} or @code{bla}. It is the responsibility |
---|
330 | of the callee to save the contents of the LR before invoking |
---|
331 | another subroutine. If the callee invokes another subroutine, |
---|
332 | it must restore the LR before executing the @code{blr} instruction |
---|
333 | to return to the caller. |
---|
334 | |
---|
335 | It is important to note that the PowerPC subroutine |
---|
336 | call and return mechanism does not automatically save and |
---|
337 | restore any registers. |
---|
338 | |
---|
339 | The LR may be accessed as special purpose register 8 (@code{SPR8}) using the |
---|
340 | "move from special register" (@code{mfspr}) and |
---|
341 | "move to special register" (@code{mtspr}) instructions. |
---|
342 | |
---|
343 | @subsection Calling Mechanism |
---|
344 | |
---|
345 | All RTEMS directives are invoked using the regular |
---|
346 | PowerPC EABI calling convention via the @code{bl} or |
---|
347 | @code{bla} instructions. |
---|
348 | |
---|
349 | @subsection Register Usage |
---|
350 | |
---|
351 | As discussed above, the call instruction does not |
---|
352 | automatically save any registers. It is the responsibility |
---|
353 | of the callee to save and restore any registers which must be preserved |
---|
354 | across subroutine calls. The callee is responsible for saving |
---|
355 | callee-preserved registers to the program stack and restoring them |
---|
356 | before returning to the caller. |
---|
357 | |
---|
358 | @subsection Parameter Passing |
---|
359 | |
---|
360 | RTEMS assumes that arguments are placed in the |
---|
361 | general purpose registers with the first argument in |
---|
362 | register 3 (@code{r3}), the second argument in general purpose |
---|
363 | register 4 (@code{r4}), and so forth until the seventh |
---|
364 | argument is in general purpose register 10 (@code{r10}). |
---|
365 | If there are more than seven arguments, then subsequent arguments |
---|
366 | are placed on the program stack. The following pseudo-code |
---|
367 | illustrates the typical sequence used to call a RTEMS directive |
---|
368 | with three (3) arguments: |
---|
369 | |
---|
370 | @example |
---|
371 | load third argument into r5 |
---|
372 | load second argument into r4 |
---|
373 | load first argument into r3 |
---|
374 | invoke directive |
---|
375 | @end example |
---|
376 | |
---|
377 | @c |
---|
378 | @c |
---|
379 | @c |
---|
380 | |
---|
381 | @section Memory Model |
---|
382 | |
---|
383 | @subsection Flat Memory Model |
---|
384 | |
---|
385 | The PowerPC architecture supports a variety of memory models. |
---|
386 | RTEMS supports the PowerPC using a flat memory model with |
---|
387 | paging disabled. In this mode, the PowerPC automatically |
---|
388 | converts every address from a logical to a physical address |
---|
389 | each time it is used. The PowerPC uses information provided |
---|
390 | in the Block Address Translation (BAT) to convert these addresses. |
---|
391 | |
---|
392 | Implementations of the PowerPC architecture may be thirty-two or sixty-four bit. |
---|
393 | The PowerPC architecture supports a flat thirty-two or sixty-four bit address |
---|
394 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
---|
395 | gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF |
---|
396 | in sixty-four bit implementations. Each address is represented |
---|
397 | by either a thirty-two bit or sixty-four bit value and is byte addressable. |
---|
398 | The address may be used to reference a single byte, half-word |
---|
399 | (2-bytes), word (4 bytes), or in sixty-four bit implementations a |
---|
400 | doubleword (8 bytes). Memory accesses within the address space are |
---|
401 | performed in big or little endian fashion by the PowerPC based |
---|
402 | upon the current setting of the Little-endian mode enable bit (LE) |
---|
403 | in the Machine State Register (MSR). While the processor is in |
---|
404 | big endian mode, memory accesses which are not properly aligned |
---|
405 | generate an "alignment exception" (vector offset 0x00600). In |
---|
406 | little endian mode, the PowerPC architecture does not require |
---|
407 | the processor to generate alignment exceptions. |
---|
408 | |
---|
409 | The following table lists the alignment requirements for a variety |
---|
410 | of data accesses: |
---|
411 | |
---|
412 | @ifset use-ascii |
---|
413 | @example |
---|
414 | @group |
---|
415 | +--------------+-----------------------+ |
---|
416 | | Data Type | Alignment Requirement | |
---|
417 | +--------------+-----------------------+ |
---|
418 | | byte | 1 | |
---|
419 | | half-word | 2 | |
---|
420 | | word | 4 | |
---|
421 | | doubleword | 8 | |
---|
422 | +--------------+-----------------------+ |
---|
423 | @end group |
---|
424 | @end example |
---|
425 | @end ifset |
---|
426 | |
---|
427 | @ifset use-tex |
---|
428 | @sp 1 |
---|
429 | @tex |
---|
430 | \centerline{\vbox{\offinterlineskip\halign{ |
---|
431 | \vrule\strut#& |
---|
432 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
---|
433 | \vrule#& |
---|
434 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
---|
435 | \vrule#\cr |
---|
436 | \noalign{\hrule} |
---|
437 | &\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule} |
---|
438 | &byte&&1&\cr\noalign{\hrule} |
---|
439 | &half-word&&2&\cr\noalign{\hrule} |
---|
440 | &word&&4&\cr\noalign{\hrule} |
---|
441 | &doubleword&&8&\cr\noalign{\hrule} |
---|
442 | }}\hfil} |
---|
443 | @end tex |
---|
444 | @end ifset |
---|
445 | |
---|
446 | @ifset use-html |
---|
447 | @html |
---|
448 | <CENTER> |
---|
449 | <TABLE COLS=2 WIDTH="60%" BORDER=2> |
---|
450 | <TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD> |
---|
451 | <TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR> |
---|
452 | <TR><TD ALIGN=center>byte</TD> |
---|
453 | <TD ALIGN=center>1</TD></TR> |
---|
454 | <TR><TD ALIGN=center>half-word</TD> |
---|
455 | <TD ALIGN=center>2</TD></TR> |
---|
456 | <TR><TD ALIGN=center>word</TD> |
---|
457 | <TD ALIGN=center>4</TD></TR> |
---|
458 | <TR><TD ALIGN=center>doubleword</TD> |
---|
459 | <TD ALIGN=center>8</TD></TR> |
---|
460 | </TABLE> |
---|
461 | </CENTER> |
---|
462 | @end html |
---|
463 | @end ifset |
---|
464 | |
---|
465 | Doubleword load and store operations are only available in |
---|
466 | PowerPC CPU models which are sixty-four bit implementations. |
---|
467 | |
---|
468 | RTEMS does not directly support any PowerPC Memory Management |
---|
469 | Units, therefore, virtual memory or segmentation systems |
---|
470 | involving the PowerPC are not supported. |
---|
471 | |
---|
472 | @c |
---|
473 | @c COPYRIGHT (c) 1989-2007. |
---|
474 | @c On-Line Applications Research Corporation (OAR). |
---|
475 | @c All rights reserved. |
---|
476 | |
---|
477 | @section Interrupt Processing |
---|
478 | |
---|
479 | Although RTEMS hides many of the processor dependent |
---|
480 | details of interrupt processing, it is important to understand |
---|
481 | how the RTEMS interrupt manager is mapped onto the processor's |
---|
482 | unique architecture. Discussed in this chapter are the PowerPC's |
---|
483 | interrupt response and control mechanisms as they pertain to |
---|
484 | RTEMS. |
---|
485 | |
---|
486 | RTEMS and associated documentation uses the terms interrupt and vector. |
---|
487 | In the PowerPC architecture, these terms correspond to exception and |
---|
488 | exception handler, respectively. The terms will be used interchangeably |
---|
489 | in this manual. |
---|
490 | |
---|
491 | @subsection Synchronous Versus Asynchronous Exceptions |
---|
492 | |
---|
493 | In the PowerPC architecture exceptions can be either precise or |
---|
494 | imprecise and either synchronous or asynchronous. Asynchronous |
---|
495 | exceptions occur when an external event interrupts the processor. |
---|
496 | Synchronous exceptions are caused by the actions of an |
---|
497 | instruction. During an exception SRR0 is used to calculate where |
---|
498 | instruction processing should resume. All instructions prior to |
---|
499 | the resume instruction will have completed execution. SRR1 is used to |
---|
500 | store the machine status. |
---|
501 | |
---|
502 | There are two asynchronous nonmaskable, highest-priority exceptions |
---|
503 | system reset and machine check. There are two asynchrononous maskable |
---|
504 | low-priority exceptions external interrupt and decrementer. Nonmaskable |
---|
505 | execptions are never delayed, therefore if two nonmaskable, asynchronous |
---|
506 | exceptions occur in immediate succession, the state information saved by |
---|
507 | the first exception may be overwritten when the subsequent exception occurs. |
---|
508 | |
---|
509 | The PowerPC arcitecure defines one imprecise exception, the imprecise |
---|
510 | floating point enabled exception. All other synchronous exceptions are |
---|
511 | precise. The synchronization occuring during asynchronous precise |
---|
512 | exceptions conforms to the requirements for context synchronization. |
---|
513 | |
---|
514 | @subsection Vectoring of Interrupt Handler |
---|
515 | |
---|
516 | Upon determining that an exception can be taken the PowerPC automatically |
---|
517 | performs the following actions: |
---|
518 | |
---|
519 | @itemize @bullet |
---|
520 | @item an instruction address is loaded into SRR0 |
---|
521 | |
---|
522 | @item bits 33-36 and 42-47 of SRR1 are loaded with information |
---|
523 | specific to the exception. |
---|
524 | |
---|
525 | @item bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding |
---|
526 | bits from the MSR. |
---|
527 | |
---|
528 | @item the MSR is set based upon the exception type. |
---|
529 | |
---|
530 | @item instruction fetch and execution resumes, using the new MSR value, at a location specific to the execption type. |
---|
531 | |
---|
532 | @end itemize |
---|
533 | |
---|
534 | If the interrupt handler was installed as an RTEMS |
---|
535 | interrupt handler, then upon receipt of the interrupt, the |
---|
536 | processor passes control to the RTEMS interrupt handler which |
---|
537 | performs the following actions: |
---|
538 | |
---|
539 | @itemize @bullet |
---|
540 | @item saves the state of the interrupted task on it's stack, |
---|
541 | |
---|
542 | @item saves all registers which are not normally preserved |
---|
543 | by the calling sequence so the user's interrupt service |
---|
544 | routine can be written in a high-level language. |
---|
545 | |
---|
546 | @item if this is the outermost (i.e. non-nested) interrupt, |
---|
547 | then the RTEMS interrupt handler switches from the current stack |
---|
548 | to the interrupt stack, |
---|
549 | |
---|
550 | @item enables exceptions, |
---|
551 | |
---|
552 | @item invokes the vectors to a user interrupt service routine (ISR). |
---|
553 | @end itemize |
---|
554 | |
---|
555 | Asynchronous interrupts are ignored while exceptions are |
---|
556 | disabled. Synchronous interrupts which occur while are |
---|
557 | disabled result in the CPU being forced into an error mode. |
---|
558 | |
---|
559 | A nested interrupt is processed similarly with the |
---|
560 | exception that the current stack need not be switched to the |
---|
561 | interrupt stack. |
---|
562 | |
---|
563 | @subsection Interrupt Levels |
---|
564 | |
---|
565 | The PowerPC architecture supports only a single external |
---|
566 | asynchronous interrupt source. This interrupt source |
---|
567 | may be enabled and disabled via the External Interrupt Enable (EE) |
---|
568 | bit in the Machine State Register (MSR). Thus only two level (enabled |
---|
569 | and disabled) of external device interrupt priorities are |
---|
570 | directly supported by the PowerPC architecture. |
---|
571 | |
---|
572 | Some PowerPC implementations include a Critical Interrupt capability |
---|
573 | which is often used to receive interrupts from high priority external |
---|
574 | devices. |
---|
575 | |
---|
576 | The RTEMS interrupt level mapping scheme for the PowerPC is not |
---|
577 | a numeric level as on most RTEMS ports. It is a bit mapping in |
---|
578 | which the least three significiant bits of the interrupt level |
---|
579 | are mapped directly to the enabling of specific interrupt |
---|
580 | sources as follows: |
---|
581 | |
---|
582 | @table @b |
---|
583 | |
---|
584 | @item Critical Interrupt |
---|
585 | Setting bit 0 (the least significant bit) of the interrupt level |
---|
586 | enables the Critical Interrupt source, if it is available on this |
---|
587 | CPU model. |
---|
588 | |
---|
589 | @item Machine Check |
---|
590 | Setting bit 1 of the interrupt level enables Machine Check execptions. |
---|
591 | |
---|
592 | @item External Interrupt |
---|
593 | Setting bit 2 of the interrupt level enables External Interrupt execptions. |
---|
594 | |
---|
595 | @end table |
---|
596 | |
---|
597 | All other bits in the RTEMS task interrupt level are ignored. |
---|
598 | |
---|
599 | @c |
---|
600 | @c |
---|
601 | @c |
---|
602 | |
---|
603 | @section Default Fatal Error Processing |
---|
604 | |
---|
605 | The default fatal error handler for this architecture performs the |
---|
606 | following actions: |
---|
607 | |
---|
608 | @itemize @bullet |
---|
609 | |
---|
610 | @item places the error code in r3, and |
---|
611 | |
---|
612 | @item executes a trap instruction which results in a Program Exception. |
---|
613 | |
---|
614 | @end itemize |
---|
615 | |
---|
616 | If the Program Exception returns, then the following actions are performed: |
---|
617 | |
---|
618 | @itemize @bullet |
---|
619 | |
---|
620 | @item disables all processor exceptions by loading a 0 into the MSR, and |
---|
621 | |
---|
622 | @item goes into an infinite loop to simulate a halt processor instruction. |
---|
623 | |
---|
624 | @end itemize |
---|
625 | |
---|
626 | @c |
---|
627 | @c |
---|
628 | @c |
---|
629 | |
---|
630 | @section Board Support Packages |
---|
631 | |
---|
632 | @subsection System Reset |
---|
633 | |
---|
634 | An RTEMS based application is initiated or |
---|
635 | re-initiated when the PowerPC processor is reset. The PowerPC |
---|
636 | architecture defines a Reset Exception, but leaves the |
---|
637 | details of the CPU state as implementation specific. Please |
---|
638 | refer to the User's Manual for the CPU model in question. |
---|
639 | |
---|
640 | In general, at power-up the PowerPC begin execution at address |
---|
641 | 0xFFF00100 in supervisor mode with all exceptions disabled. For |
---|
642 | soft resets, the CPU will vector to either 0xFFF00100 or 0x00000100 |
---|
643 | depending upon the setting of the Exception Prefix bit in the MSR. |
---|
644 | If during a soft reset, a Machine Check Exception occurs, then the |
---|
645 | CPU may execute a hard reset. |
---|
646 | |
---|
647 | @subsection Processor Initialization |
---|
648 | |
---|
649 | If this PowerPC implementation supports on-chip caching |
---|
650 | and this is to be utilized, then it should be enabled during the |
---|
651 | reset application initialization code. On-chip caching has been |
---|
652 | observed to prevent some emulators from working properly, so it |
---|
653 | may be necessary to run with caching disabled to use these emulators. |
---|
654 | |
---|
655 | In addition to the requirements described in the |
---|
656 | @b{Board Support Packages} chapter of the RTEMS C |
---|
657 | Applications User's Manual for the reset code |
---|
658 | which is executed before the call to @code{rtems_initialize_executive}, |
---|
659 | the PowrePC version has the following specific requirements: |
---|
660 | |
---|
661 | @itemize @bullet |
---|
662 | @item Must leave the PR bit of the Machine State Register (MSR) set |
---|
663 | to 0 so the PowerPC remains in the supervisor state. |
---|
664 | |
---|
665 | @item Must set stack pointer (sp or r1) such that a minimum stack |
---|
666 | size of MINIMUM_STACK_SIZE bytes is provided for the RTEMS initialization |
---|
667 | sequence. |
---|
668 | |
---|
669 | @item Must disable all external interrupts (i.e. clear the EI (EE) |
---|
670 | bit of the machine state register). |
---|
671 | |
---|
672 | @item Must enable traps so window overflow and underflow |
---|
673 | conditions can be properly handled. |
---|
674 | |
---|
675 | @item Must initialize the PowerPC's initial Exception Table with default |
---|
676 | handlers. |
---|
677 | |
---|
678 | @end itemize |
---|