1 | @c |
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2 | @c COPYRIGHT (c) 1989-2007. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | |
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6 | @ifinfo |
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7 | @end ifinfo |
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8 | @chapter PowerPC Specific Information |
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9 | |
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10 | This chapter discusses the PowerPC architecture dependencies |
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11 | in this port of RTEMS. The PowerPC family has a wide variety |
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12 | of implementations by a range of vendors. Consequently, |
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13 | there are many, many CPU models within it. |
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14 | |
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15 | It is highly recommended that the PowerPC RTEMS |
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16 | application developer obtain and become familiar with the |
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17 | documentation for the processor being used as well as the |
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18 | specification for the revision of the PowerPC architecture which |
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19 | corresponds to that processor. |
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20 | |
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21 | @subheading PowerPC Architecture Documents |
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22 | |
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23 | For information on the PowerPC architecture, refer to |
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24 | the following documents available from Motorola and IBM: |
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25 | |
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26 | @itemize @bullet |
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27 | |
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28 | @item @cite{PowerPC Microprocessor Family: The Programming Environment} |
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29 | (Motorola Document MPRPPCFPE-01). |
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30 | |
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31 | @item @cite{IBM PPC403GB Embedded Controller User's Manual}. |
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32 | |
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33 | @item @cite{PoweRisControl MPC500 Family RCPU RISC Central Processing |
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34 | Unit Reference Manual} (Motorola Document RCPUURM/AD). |
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35 | |
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36 | @item @cite{PowerPC 601 RISC Microprocessor User's Manual} |
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37 | (Motorola Document MPR601UM/AD). |
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38 | |
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39 | @item @cite{PowerPC 603 RISC Microprocessor User's Manual} |
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40 | (Motorola Document MPR603UM/AD). |
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41 | |
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42 | @item @cite{PowerPC 603e RISC Microprocessor User's Manual} |
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43 | (Motorola Document MPR603EUM/AD). |
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44 | |
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45 | @item @cite{PowerPC 604 RISC Microprocessor User's Manual} |
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46 | (Motorola Document MPR604UM/AD). |
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47 | |
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48 | @item @cite{PowerPC MPC821 Portable Systems Microprocessor User's Manual} |
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49 | (Motorola Document MPC821UM/AD). |
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50 | |
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51 | @item @cite{PowerQUICC MPC860 User's Manual} (Motorola Document MPC860UM/AD). |
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52 | |
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53 | @end itemize |
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54 | |
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55 | Motorola maintains an on-line electronic library for the PowerPC |
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56 | at the following URL: |
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57 | |
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58 | @itemize @code{ } |
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59 | @item @cite{http://www.mot.com/powerpc/library/library.html} |
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60 | @end itemize |
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61 | |
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62 | This site has a a wealth of information and examples. Many of the |
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63 | manuals are available from that site in electronic format. |
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64 | |
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65 | @subheading PowerPC Processor Simulator Information |
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66 | |
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67 | PSIM is a program which emulates the Instruction Set Architecture |
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68 | of the PowerPC microprocessor family. It is reely available in source |
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69 | code form under the terms of the GNU General Public License (version |
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70 | 2 or later). PSIM can be integrated with the GNU Debugger (gdb) to |
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71 | execute and debug PowerPC executables on non-PowerPC hosts. PSIM |
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72 | supports the addition of user provided device models which can be |
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73 | used to allow one to develop and debug embedded applications using |
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74 | the simulator. |
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75 | |
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76 | The latest version of PSIM is included in GDB and enabled on pre-built |
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77 | binaries provided by the RTEMS Project. |
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78 | |
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79 | @c |
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80 | @c |
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81 | @c |
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82 | @section CPU Model Dependent Features |
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83 | |
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84 | This section presents the set of features which vary |
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85 | across PowerPC implementations and are of importance to RTEMS. |
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86 | The set of CPU model feature macros are defined in the file |
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87 | @code{cpukit/score/cpu/powerpc/powerpc.h} based upon the particular CPU |
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88 | model specified on the compilation command line. |
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89 | |
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90 | @subsection Alignment |
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91 | |
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92 | The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment |
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93 | requirement for data types on a byte boundary. This value is used |
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94 | to derive the alignment restrictions for memory allocated from |
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95 | regions and partitions. |
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96 | |
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97 | @subsection Cache Alignment |
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98 | |
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99 | The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is |
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100 | used to align the entry point of critical routines so that as much code |
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101 | as possible can be retrieved with the initial read into cache. This |
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102 | is done for the interrupt handler as well as the context switch routines. |
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103 | |
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104 | In addition, the "shortcut" data structure used by the PowerPC implementation |
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105 | to ease access to data elements frequently accessed by RTEMS routines |
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106 | implemented in assembly language is aligned using this value. |
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107 | |
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108 | @subsection Maximum Interrupts |
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109 | |
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110 | The macro PPC_INTERRUPT_MAX is set to the number of exception sources |
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111 | supported by this PowerPC model. |
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112 | |
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113 | @subsection Has Double Precision Floating Point |
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114 | |
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115 | The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model |
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116 | has support for double precision floating point numbers. This is |
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117 | important because the floating point registers need only be four bytes |
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118 | wide (not eight) if double precision is not supported. |
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119 | |
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120 | @subsection Critical Interrupts |
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121 | |
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122 | The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model |
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123 | has the Critical Interrupt capability as defined by the IBM 403 models. |
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124 | |
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125 | @subsection Use Multiword Load/Store Instructions |
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126 | |
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127 | The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and |
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128 | store instructions should be used to perform context switch operations. |
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129 | The relative efficiency of multiword load and store instructions versus |
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130 | an equivalent set of single word load and store instructions varies based |
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131 | upon the PowerPC model. |
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132 | |
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133 | @subsection Instruction Cache Size |
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134 | |
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135 | The macro PPC_I_CACHE is set to the size in bytes of the instruction cache. |
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136 | |
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137 | @subsection Data Cache Size |
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138 | |
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139 | The macro PPC_D_CACHE is set to the size in bytes of the data cache. |
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140 | |
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141 | @subsection Debug Model |
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142 | |
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143 | The macro PPC_DEBUG_MODEL is set to indicate the debug support features |
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144 | present in this CPU model. The following debug support feature sets |
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145 | are currently supported: |
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146 | |
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147 | @table @b |
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148 | |
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149 | @item @code{PPC_DEBUG_MODEL_STANDARD} |
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150 | indicates that the single-step trace enable (SE) and branch trace |
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151 | enable (BE) bits in the MSR are supported by this CPU model. |
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152 | |
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153 | @item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY} |
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154 | indicates that only the single-step trace enable (SE) bit in the MSR |
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155 | is supported by this CPU model. |
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156 | |
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157 | @item @code{PPC_DEBUG_MODEL_IBM4xx} |
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158 | indicates that the debug exception enable (DE) bit in the MSR is supported |
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159 | by this CPU model. At this time, this particular debug feature set |
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160 | has only been seen in the IBM 4xx series. |
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161 | |
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162 | @end table |
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163 | |
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164 | @subsubsection Low Power Model |
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165 | |
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166 | The macro PPC_LOW_POWER_MODE is set to indicate the low power model |
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167 | supported by this CPU model. The following low power modes are currently |
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168 | supported. |
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169 | |
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170 | @table @b |
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171 | |
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172 | @item @code{PPC_LOW_POWER_MODE_NONE} |
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173 | indicates that this CPU model has no low power mode support. |
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174 | |
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175 | @item @code{PPC_LOW_POWER_MODE_STANDARD} |
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176 | indicates that this CPU model follows the low power model defined for |
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177 | the PPC603e. |
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178 | |
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179 | @end table |
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180 | |
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181 | @c |
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182 | @c |
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183 | @c |
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184 | @section Multilibs |
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185 | |
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186 | The following multilibs are available: |
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187 | |
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188 | @enumerate |
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189 | @item @code{.}: 32-bit PowerPC with FPU |
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190 | @item @code{nof}: 32-bit PowerPC with software floating point support |
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191 | @item @code{m403}: Instruction set for PPC403 with FPU |
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192 | @item @code{m505}: Instruction set for MPC505 with FPU |
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193 | @item @code{m603e}: Instruction set for MPC603e with FPU |
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194 | @item @code{m603e/nof}: Instruction set for MPC603e with software floating |
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195 | point support |
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196 | @item @code{m604}: Instruction set for MPC604 with FPU |
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197 | @item @code{m604/nof}: Instruction set for MPC604 with software floating point |
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198 | support |
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199 | @item @code{m860}: Instruction set for MPC860 with FPU |
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200 | @item @code{m7400}: Instruction set for MPC7500 with FPU |
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201 | @item @code{m7400/nof}: Instruction set for MPC7500 with software floating |
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202 | point support |
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203 | @item @code{m8540}: Instruction set for e200, e500 and e500v2 cores with |
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204 | single-precision FPU and SPE |
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205 | @item @code{m8540/gprsdouble}: Instruction set for e200, e500 and e500v2 cores |
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206 | with double-precision FPU and SPE |
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207 | @item @code{m8540/nof/nospe}: Instruction set for e200, e500 and e500v2 cores |
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208 | with software floating point support and no SPE |
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209 | @item @code{me6500/m32}: 32-bit instruction set for e6500 core with FPU and |
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210 | AltiVec |
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211 | @item @code{me6500/m32/nof/noaltivec}: 32-bit instruction set for e6500 core |
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212 | with software floating point support and no AltiVec |
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213 | @end enumerate |
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214 | |
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215 | @c |
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216 | @c |
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217 | @c |
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218 | |
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219 | @section Calling Conventions |
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220 | |
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221 | RTEMS supports the Embedded Application Binary Interface (EABI) |
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222 | calling convention. Documentation for EABI is available by sending |
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223 | a message with a subject line of "EABI" to eabi@@goth.sis.mot.com. |
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224 | |
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225 | @subsection Programming Model |
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226 | |
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227 | This section discusses the programming model for the |
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228 | PowerPC architecture. |
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229 | |
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230 | @subsubsection Non-Floating Point Registers |
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231 | |
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232 | The PowerPC architecture defines thirty-two non-floating point registers |
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233 | directly visible to the programmer. In thirty-two bit implementations, each |
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234 | register is thirty-two bits wide. In sixty-four bit implementations, each |
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235 | register is sixty-four bits wide. |
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236 | |
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237 | These registers are referred to as @code{gpr0} to @code{gpr31}. |
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238 | |
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239 | Some of the registers serve defined roles in the EABI programming model. |
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240 | The following table describes the role of each of these registers: |
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241 | |
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242 | @ifset use-ascii |
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243 | @example |
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244 | @group |
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245 | +---------------+----------------+------------------------------+ |
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246 | | Register Name | Alternate Name | Description | |
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247 | +---------------+----------------+------------------------------+ |
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248 | | r1 | sp | stack pointer | |
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249 | +---------------+----------------+------------------------------+ |
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250 | | | | global pointer to the Small | |
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251 | | r2 | na | Constant Area (SDA2) | |
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252 | +---------------+----------------+------------------------------+ |
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253 | | r3 - r12 | na | parameter and result passing | |
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254 | +---------------+----------------+------------------------------+ |
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255 | | | | global pointer to the Small | |
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256 | | r13 | na | Data Area (SDA) | |
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257 | +---------------+----------------+------------------------------+ |
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258 | @end group |
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259 | @end example |
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260 | @end ifset |
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261 | |
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262 | @ifset use-tex |
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263 | @sp 1 |
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264 | @tex |
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265 | \centerline{\vbox{\offinterlineskip\halign{ |
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266 | \vrule\strut#& |
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267 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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268 | \vrule#& |
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269 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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270 | \vrule#& |
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271 | \hbox to 2.50in{\enskip\hfil#\hfil}& |
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272 | \vrule#\cr |
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273 | \noalign{\hrule} |
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274 | &\bf Register Name &&\bf Alternate Names&&\bf Description&\cr\noalign{\hrule} |
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275 | &r1&&sp&&stack pointer&\cr\noalign{\hrule} |
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276 | &r2&&NA&&global pointer to the Small&\cr |
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277 | &&&&&Constant Area (SDA2)&\cr\noalign{\hrule} |
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278 | &r3 - r12&&NA&¶meter and result passing&\cr\noalign{\hrule} |
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279 | &r13&&NA&&global pointer to the Small&\cr |
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280 | &&&&&Data Area (SDA2)&\cr\noalign{\hrule} |
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281 | }}\hfil} |
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282 | @end tex |
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283 | @end ifset |
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284 | |
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285 | @ifset use-html |
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286 | @html |
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287 | <CENTER> |
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288 | <TABLE COLS=3 WIDTH="80%" BORDER=2> |
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289 | <TR><TD ALIGN=center><STRONG>Register Name</STRONG></TD> |
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290 | <TD ALIGN=center><STRONG>Alternate Name</STRONG></TD> |
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291 | <TD ALIGN=center><STRONG>Description</STRONG></TD></TR> |
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292 | <TR><TD ALIGN=center>r1</TD> |
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293 | <TD ALIGN=center>sp</TD> |
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294 | <TD ALIGN=center>stack pointer</TD></TR> |
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295 | <TR><TD ALIGN=center>r2</TD> |
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296 | <TD ALIGN=center>na</TD> |
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297 | <TD ALIGN=center>global pointer to the Small Constant Area (SDA2)</TD></TR> |
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298 | <TR><TD ALIGN=center>r3 - r12</TD> |
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299 | <TD ALIGN=center>NA</TD> |
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300 | <TD ALIGN=center>parameter and result passing</TD></TR> |
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301 | <TR><TD ALIGN=center>r13</TD> |
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302 | <TD ALIGN=center>NA</TD> |
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303 | <TD ALIGN=center>global pointer to the Small Data Area (SDA)</TD></TR> |
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304 | </TABLE> |
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305 | </CENTER> |
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306 | @end html |
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307 | @end ifset |
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308 | |
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309 | |
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310 | @subsubsection Floating Point Registers |
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311 | |
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312 | The PowerPC architecture includes thirty-two, sixty-four bit |
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313 | floating point registers. All PowerPC floating point instructions |
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314 | interpret these registers as 32 double precision floating point registers, |
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315 | regardless of whether the processor has 64-bit or 32-bit implementation. |
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316 | |
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317 | The floating point status and control register (fpscr) records exceptions |
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318 | and the type of result generated by floating-point operations. |
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319 | Additionally, it controls the rounding mode of operations and allows the |
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320 | reporting of floating exceptions to be enabled or disabled. |
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321 | |
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322 | @subsubsection Special Registers |
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323 | |
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324 | The PowerPC architecture includes a number of special registers |
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325 | which are critical to the programming model: |
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326 | |
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327 | @table @b |
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328 | |
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329 | @item Machine State Register |
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330 | |
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331 | The MSR contains the processor mode, power management mode, endian mode, |
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332 | exception information, privilege level, floating point available and |
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333 | floating point excepiton mode, address translation information and |
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334 | the exception prefix. |
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335 | |
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336 | @item Link Register |
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337 | |
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338 | The LR contains the return address after a function call. This register |
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339 | must be saved before a subsequent subroutine call can be made. The |
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340 | use of this register is discussed further in the @b{Call and Return |
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341 | Mechanism} section below. |
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342 | |
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343 | @item Count Register |
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344 | |
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345 | The CTR contains the iteration variable for some loops. It may also be used |
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346 | for indirect function calls and jumps. |
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347 | |
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348 | @end table |
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349 | |
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350 | @subsection Call and Return Mechanism |
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351 | |
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352 | The PowerPC architecture supports a simple yet effective call |
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353 | and return mechanism. A subroutine is invoked |
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354 | via the "branch and link" (@code{bl}) and |
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355 | "brank and link absolute" (@code{bla}) |
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356 | instructions. This instructions place the return address |
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357 | in the Link Register (LR). The callee returns to the caller by |
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358 | executing a "branch unconditional to the link register" (@code{blr}) |
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359 | instruction. Thus the callee returns to the caller via a jump |
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360 | to the return address which is stored in the LR. |
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361 | |
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362 | The previous contents of the LR are not automatically saved |
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363 | by either the @code{bl} or @code{bla}. It is the responsibility |
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364 | of the callee to save the contents of the LR before invoking |
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365 | another subroutine. If the callee invokes another subroutine, |
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366 | it must restore the LR before executing the @code{blr} instruction |
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367 | to return to the caller. |
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368 | |
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369 | It is important to note that the PowerPC subroutine |
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370 | call and return mechanism does not automatically save and |
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371 | restore any registers. |
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372 | |
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373 | The LR may be accessed as special purpose register 8 (@code{SPR8}) using the |
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374 | "move from special register" (@code{mfspr}) and |
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375 | "move to special register" (@code{mtspr}) instructions. |
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376 | |
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377 | @subsection Calling Mechanism |
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378 | |
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379 | All RTEMS directives are invoked using the regular |
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380 | PowerPC EABI calling convention via the @code{bl} or |
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381 | @code{bla} instructions. |
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382 | |
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383 | @subsection Register Usage |
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384 | |
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385 | As discussed above, the call instruction does not |
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386 | automatically save any registers. It is the responsibility |
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387 | of the callee to save and restore any registers which must be preserved |
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388 | across subroutine calls. The callee is responsible for saving |
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389 | callee-preserved registers to the program stack and restoring them |
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390 | before returning to the caller. |
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391 | |
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392 | @subsection Parameter Passing |
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393 | |
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394 | RTEMS assumes that arguments are placed in the |
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395 | general purpose registers with the first argument in |
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396 | register 3 (@code{r3}), the second argument in general purpose |
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397 | register 4 (@code{r4}), and so forth until the seventh |
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398 | argument is in general purpose register 10 (@code{r10}). |
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399 | If there are more than seven arguments, then subsequent arguments |
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400 | are placed on the program stack. The following pseudo-code |
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401 | illustrates the typical sequence used to call a RTEMS directive |
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402 | with three (3) arguments: |
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403 | |
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404 | @example |
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405 | load third argument into r5 |
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406 | load second argument into r4 |
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407 | load first argument into r3 |
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408 | invoke directive |
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409 | @end example |
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410 | |
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411 | @c |
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412 | @c |
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413 | @c |
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414 | |
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415 | @section Memory Model |
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416 | |
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417 | @subsection Flat Memory Model |
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418 | |
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419 | The PowerPC architecture supports a variety of memory models. |
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420 | RTEMS supports the PowerPC using a flat memory model with |
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421 | paging disabled. In this mode, the PowerPC automatically |
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422 | converts every address from a logical to a physical address |
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423 | each time it is used. The PowerPC uses information provided |
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424 | in the Block Address Translation (BAT) to convert these addresses. |
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425 | |
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426 | Implementations of the PowerPC architecture may be thirty-two or sixty-four bit. |
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427 | The PowerPC architecture supports a flat thirty-two or sixty-four bit address |
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428 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
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429 | gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF |
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430 | in sixty-four bit implementations. Each address is represented |
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431 | by either a thirty-two bit or sixty-four bit value and is byte addressable. |
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432 | The address may be used to reference a single byte, half-word |
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433 | (2-bytes), word (4 bytes), or in sixty-four bit implementations a |
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434 | doubleword (8 bytes). Memory accesses within the address space are |
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435 | performed in big or little endian fashion by the PowerPC based |
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436 | upon the current setting of the Little-endian mode enable bit (LE) |
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437 | in the Machine State Register (MSR). While the processor is in |
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438 | big endian mode, memory accesses which are not properly aligned |
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439 | generate an "alignment exception" (vector offset 0x00600). In |
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440 | little endian mode, the PowerPC architecture does not require |
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441 | the processor to generate alignment exceptions. |
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442 | |
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443 | The following table lists the alignment requirements for a variety |
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444 | of data accesses: |
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445 | |
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446 | @ifset use-ascii |
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447 | @example |
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448 | @group |
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449 | +--------------+-----------------------+ |
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450 | | Data Type | Alignment Requirement | |
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451 | +--------------+-----------------------+ |
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452 | | byte | 1 | |
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453 | | half-word | 2 | |
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454 | | word | 4 | |
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455 | | doubleword | 8 | |
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456 | +--------------+-----------------------+ |
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457 | @end group |
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458 | @end example |
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459 | @end ifset |
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460 | |
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461 | @ifset use-tex |
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462 | @sp 1 |
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463 | @tex |
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464 | \centerline{\vbox{\offinterlineskip\halign{ |
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465 | \vrule\strut#& |
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466 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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467 | \vrule#& |
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468 | \hbox to 1.75in{\enskip\hfil#\hfil}& |
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469 | \vrule#\cr |
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470 | \noalign{\hrule} |
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471 | &\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule} |
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472 | &byte&&1&\cr\noalign{\hrule} |
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473 | &half-word&&2&\cr\noalign{\hrule} |
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474 | &word&&4&\cr\noalign{\hrule} |
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475 | &doubleword&&8&\cr\noalign{\hrule} |
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476 | }}\hfil} |
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477 | @end tex |
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478 | @end ifset |
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479 | |
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480 | @ifset use-html |
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481 | @html |
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482 | <CENTER> |
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483 | <TABLE COLS=2 WIDTH="60%" BORDER=2> |
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484 | <TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD> |
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485 | <TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR> |
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486 | <TR><TD ALIGN=center>byte</TD> |
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487 | <TD ALIGN=center>1</TD></TR> |
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488 | <TR><TD ALIGN=center>half-word</TD> |
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489 | <TD ALIGN=center>2</TD></TR> |
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490 | <TR><TD ALIGN=center>word</TD> |
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491 | <TD ALIGN=center>4</TD></TR> |
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492 | <TR><TD ALIGN=center>doubleword</TD> |
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493 | <TD ALIGN=center>8</TD></TR> |
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494 | </TABLE> |
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495 | </CENTER> |
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496 | @end html |
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497 | @end ifset |
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498 | |
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499 | Doubleword load and store operations are only available in |
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500 | PowerPC CPU models which are sixty-four bit implementations. |
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501 | |
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502 | RTEMS does not directly support any PowerPC Memory Management |
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503 | Units, therefore, virtual memory or segmentation systems |
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504 | involving the PowerPC are not supported. |
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505 | |
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506 | @c |
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507 | @c COPYRIGHT (c) 1989-2007. |
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508 | @c On-Line Applications Research Corporation (OAR). |
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509 | @c All rights reserved. |
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510 | |
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511 | @section Interrupt Processing |
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512 | |
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513 | Although RTEMS hides many of the processor dependent |
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514 | details of interrupt processing, it is important to understand |
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515 | how the RTEMS interrupt manager is mapped onto the processor's |
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516 | unique architecture. Discussed in this chapter are the PowerPC's |
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517 | interrupt response and control mechanisms as they pertain to |
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518 | RTEMS. |
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519 | |
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520 | RTEMS and associated documentation uses the terms interrupt and vector. |
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521 | In the PowerPC architecture, these terms correspond to exception and |
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522 | exception handler, respectively. The terms will be used interchangeably |
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523 | in this manual. |
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524 | |
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525 | @subsection Synchronous Versus Asynchronous Exceptions |
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526 | |
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527 | In the PowerPC architecture exceptions can be either precise or |
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528 | imprecise and either synchronous or asynchronous. Asynchronous |
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529 | exceptions occur when an external event interrupts the processor. |
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530 | Synchronous exceptions are caused by the actions of an |
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531 | instruction. During an exception SRR0 is used to calculate where |
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532 | instruction processing should resume. All instructions prior to |
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533 | the resume instruction will have completed execution. SRR1 is used to |
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534 | store the machine status. |
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535 | |
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536 | There are two asynchronous nonmaskable, highest-priority exceptions |
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537 | system reset and machine check. There are two asynchrononous maskable |
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538 | low-priority exceptions external interrupt and decrementer. Nonmaskable |
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539 | execptions are never delayed, therefore if two nonmaskable, asynchronous |
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540 | exceptions occur in immediate succession, the state information saved by |
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541 | the first exception may be overwritten when the subsequent exception occurs. |
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542 | |
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543 | The PowerPC arcitecure defines one imprecise exception, the imprecise |
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544 | floating point enabled exception. All other synchronous exceptions are |
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545 | precise. The synchronization occuring during asynchronous precise |
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546 | exceptions conforms to the requirements for context synchronization. |
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547 | |
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548 | @subsection Vectoring of Interrupt Handler |
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549 | |
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550 | Upon determining that an exception can be taken the PowerPC automatically |
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551 | performs the following actions: |
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552 | |
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553 | @itemize @bullet |
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554 | @item an instruction address is loaded into SRR0 |
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555 | |
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556 | @item bits 33-36 and 42-47 of SRR1 are loaded with information |
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557 | specific to the exception. |
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558 | |
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559 | @item bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding |
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560 | bits from the MSR. |
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561 | |
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562 | @item the MSR is set based upon the exception type. |
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563 | |
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564 | @item instruction fetch and execution resumes, using the new MSR value, at a location specific to the execption type. |
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565 | |
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566 | @end itemize |
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567 | |
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568 | If the interrupt handler was installed as an RTEMS |
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569 | interrupt handler, then upon receipt of the interrupt, the |
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570 | processor passes control to the RTEMS interrupt handler which |
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571 | performs the following actions: |
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572 | |
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573 | @itemize @bullet |
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574 | @item saves the state of the interrupted task on it's stack, |
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575 | |
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576 | @item saves all registers which are not normally preserved |
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577 | by the calling sequence so the user's interrupt service |
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578 | routine can be written in a high-level language. |
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579 | |
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580 | @item if this is the outermost (i.e. non-nested) interrupt, |
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581 | then the RTEMS interrupt handler switches from the current stack |
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582 | to the interrupt stack, |
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583 | |
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584 | @item enables exceptions, |
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585 | |
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586 | @item invokes the vectors to a user interrupt service routine (ISR). |
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587 | @end itemize |
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588 | |
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589 | Asynchronous interrupts are ignored while exceptions are |
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590 | disabled. Synchronous interrupts which occur while are |
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591 | disabled result in the CPU being forced into an error mode. |
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592 | |
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593 | A nested interrupt is processed similarly with the |
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594 | exception that the current stack need not be switched to the |
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595 | interrupt stack. |
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596 | |
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597 | @subsection Interrupt Levels |
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598 | |
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599 | The PowerPC architecture supports only a single external |
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600 | asynchronous interrupt source. This interrupt source |
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601 | may be enabled and disabled via the External Interrupt Enable (EE) |
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602 | bit in the Machine State Register (MSR). Thus only two level (enabled |
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603 | and disabled) of external device interrupt priorities are |
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604 | directly supported by the PowerPC architecture. |
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605 | |
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606 | Some PowerPC implementations include a Critical Interrupt capability |
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607 | which is often used to receive interrupts from high priority external |
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608 | devices. |
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609 | |
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610 | The RTEMS interrupt level mapping scheme for the PowerPC is not |
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611 | a numeric level as on most RTEMS ports. It is a bit mapping in |
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612 | which the least three significiant bits of the interrupt level |
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613 | are mapped directly to the enabling of specific interrupt |
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614 | sources as follows: |
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615 | |
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616 | @table @b |
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617 | |
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618 | @item Critical Interrupt |
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619 | Setting bit 0 (the least significant bit) of the interrupt level |
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620 | enables the Critical Interrupt source, if it is available on this |
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621 | CPU model. |
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622 | |
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623 | @item Machine Check |
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624 | Setting bit 1 of the interrupt level enables Machine Check execptions. |
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625 | |
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626 | @item External Interrupt |
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627 | Setting bit 2 of the interrupt level enables External Interrupt execptions. |
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628 | |
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629 | @end table |
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630 | |
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631 | All other bits in the RTEMS task interrupt level are ignored. |
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632 | |
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633 | @c |
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634 | @c |
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635 | @c |
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636 | |
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637 | @section Default Fatal Error Processing |
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638 | |
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639 | The default fatal error handler for this architecture performs the |
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640 | following actions: |
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641 | |
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642 | @itemize @bullet |
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643 | |
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644 | @item places the error code in r3, and |
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645 | |
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646 | @item executes a trap instruction which results in a Program Exception. |
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647 | |
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648 | @end itemize |
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649 | |
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650 | If the Program Exception returns, then the following actions are performed: |
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651 | |
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652 | @itemize @bullet |
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653 | |
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654 | @item disables all processor exceptions by loading a 0 into the MSR, and |
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655 | |
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656 | @item goes into an infinite loop to simulate a halt processor instruction. |
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657 | |
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658 | @end itemize |
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659 | |
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660 | @section Symmetric Multiprocessing |
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661 | |
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662 | SMP is supported. Available platforms are the Freescale QorIQ P series (e.g. |
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663 | P1020) and T series (e.g. T2080, T4240). |
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664 | |
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665 | @section Thread-Local Storage |
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666 | |
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667 | Thread-local storage is supported. |
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668 | |
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669 | @c |
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670 | @c |
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671 | @c |
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672 | |
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673 | @section Board Support Packages |
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674 | |
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675 | @subsection System Reset |
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676 | |
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677 | An RTEMS based application is initiated or |
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678 | re-initiated when the PowerPC processor is reset. The PowerPC |
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679 | architecture defines a Reset Exception, but leaves the |
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680 | details of the CPU state as implementation specific. Please |
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681 | refer to the User's Manual for the CPU model in question. |
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682 | |
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683 | In general, at power-up the PowerPC begin execution at address |
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684 | 0xFFF00100 in supervisor mode with all exceptions disabled. For |
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685 | soft resets, the CPU will vector to either 0xFFF00100 or 0x00000100 |
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686 | depending upon the setting of the Exception Prefix bit in the MSR. |
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687 | If during a soft reset, a Machine Check Exception occurs, then the |
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688 | CPU may execute a hard reset. |
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689 | |
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690 | @subsection Processor Initialization |
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691 | |
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692 | If this PowerPC implementation supports on-chip caching |
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693 | and this is to be utilized, then it should be enabled during the |
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694 | reset application initialization code. On-chip caching has been |
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695 | observed to prevent some emulators from working properly, so it |
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696 | may be necessary to run with caching disabled to use these emulators. |
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697 | |
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698 | In addition to the requirements described in the |
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699 | @b{Board Support Packages} chapter of the RTEMS C |
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700 | Applications User's Manual for the reset code |
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701 | which is executed before the call to @code{rtems_initialize_executive}, |
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702 | the PowrePC version has the following specific requirements: |
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703 | |
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704 | @itemize @bullet |
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705 | @item Must leave the PR bit of the Machine State Register (MSR) set |
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706 | to 0 so the PowerPC remains in the supervisor state. |
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707 | |
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708 | @item Must set stack pointer (sp or r1) such that a minimum stack |
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709 | size of MINIMUM_STACK_SIZE bytes is provided for the RTEMS initialization |
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710 | sequence. |
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711 | |
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712 | @item Must disable all external interrupts (i.e. clear the EI (EE) |
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713 | bit of the machine state register). |
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714 | |
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715 | @item Must enable traps so window overflow and underflow |
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716 | conditions can be properly handled. |
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717 | |
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718 | @item Must initialize the PowerPC's initial Exception Table with default |
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719 | handlers. |
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720 | |
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721 | @end itemize |
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