source: rtems/doc/cpu_supplement/or1k.t @ b088292

4.115
Last change on this file since b088292 was b088292, checked in by Hesham ALMatary <heshamelmatary@…>, on Aug 16, 2014 at 4:30:19 PM

Add new documentation section for OpenRISC CPU architecture.

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1@c
2@c  COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
3@c  All rights reserved.
4
5@ifinfo
6@end ifinfo
7@chapter OpenRISC 1000 Specific Information
8
9This chapter discusses the
10@uref{http://opencores.org/or1k/Main_Page, OpenRISC 1000 architecture}
11dependencies in this port of RTEMS. There are many implementations
12for OpenRISC like or1200 and mor1kx. Currently RTEMS supports basic
13features that all implementations should have.
14
15@subheading Architecture Documents
16
17For information on the OpenRISC 1000 architecture refer to the
18@uref{http://openrisc.github.io/or1k.html,OpenRISC 1000 architecture manual}.
19
20@section Calling Conventions
21
22Please refer to the
23@uref{http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882,Function Calling Sequence}.
24
25@subsection Floating Point Unit
26
27A floating point unit is currently not supported.
28
29@section Memory Model
30
31A flat 32-bit memory model is supported.
32
33@section Interrupt Processing
34
35OpenRISC 1000 architecture has 13 exception types:
36
37@itemize @bullet
38
39@item Reset
40@item Bus Error
41@item Data Page Fault
42@item Instruction Page Fault
43@item Tick Timer
44@item Alignment
45@item Illegal Instruction
46@item External Interrupt
47@item D-TLB Miss
48@item I-TLB Miss
49@item Range
50@item System Call
51@item Floating Point
52@item Trap
53
54@end itemize
55
56@subsection Interrupt Levels
57
58There are only two levels: interrupts enabled and interrupts disabled.
59
60@subsection Interrupt Stack
61
62OpenRISC RTEMS port uses RTEMS SW interrupt stack.
63The stack for interrupts is allocated during interrupt driver initilization.
64When an  interrup entered, the _ISR_Handler routine is resposible for
65switching from the interrupted task stack to RTEMS SW interrupt stack.
66
67@section Default Fatal Error Processing
68
69The default fatal error handler for this architecture performs the
70following actions:
71
72@itemize @bullet
73@item disables operating system supported interrupts (IRQ),
74@item places the error code in @code{r0}, and
75@item executes an infinite loop to simulate a halt processor instruction.
76@end itemize
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