[b088292] | 1 | @c |
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| 2 | @c COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
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| 3 | @c All rights reserved. |
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| 4 | |
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| 5 | @ifinfo |
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| 6 | @end ifinfo |
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| 7 | @chapter OpenRISC 1000 Specific Information |
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| 8 | |
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| 9 | This chapter discusses the |
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| 10 | @uref{http://opencores.org/or1k/Main_Page, OpenRISC 1000 architecture} |
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| 11 | dependencies in this port of RTEMS. There are many implementations |
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| 12 | for OpenRISC like or1200 and mor1kx. Currently RTEMS supports basic |
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| 13 | features that all implementations should have. |
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| 14 | |
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| 15 | @subheading Architecture Documents |
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| 16 | |
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| 17 | For information on the OpenRISC 1000 architecture refer to the |
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| 18 | @uref{http://openrisc.github.io/or1k.html,OpenRISC 1000 architecture manual}. |
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| 19 | |
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| 20 | @section Calling Conventions |
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| 21 | |
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| 22 | Please refer to the |
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| 23 | @uref{http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882,Function Calling Sequence}. |
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| 24 | |
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| 25 | @subsection Floating Point Unit |
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| 26 | |
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| 27 | A floating point unit is currently not supported. |
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| 28 | |
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| 29 | @section Memory Model |
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| 30 | |
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| 31 | A flat 32-bit memory model is supported. |
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| 32 | |
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| 33 | @section Interrupt Processing |
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| 34 | |
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| 35 | OpenRISC 1000 architecture has 13 exception types: |
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| 36 | |
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| 37 | @itemize @bullet |
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| 38 | |
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| 39 | @item Reset |
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| 40 | @item Bus Error |
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| 41 | @item Data Page Fault |
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| 42 | @item Instruction Page Fault |
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| 43 | @item Tick Timer |
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| 44 | @item Alignment |
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| 45 | @item Illegal Instruction |
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| 46 | @item External Interrupt |
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| 47 | @item D-TLB Miss |
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| 48 | @item I-TLB Miss |
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| 49 | @item Range |
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| 50 | @item System Call |
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| 51 | @item Floating Point |
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| 52 | @item Trap |
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| 53 | |
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| 54 | @end itemize |
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| 55 | |
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| 56 | @subsection Interrupt Levels |
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| 57 | |
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| 58 | There are only two levels: interrupts enabled and interrupts disabled. |
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| 59 | |
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| 60 | @subsection Interrupt Stack |
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| 61 | |
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[a7ec6fa] | 62 | The OpenRISC RTEMS port uses a dedicated software interrupt stack. |
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| 63 | The stack for interrupts is allocated during interrupt driver initialization. |
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| 64 | When an interrupt is entered, the _ISR_Handler routine is responsible for |
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| 65 | switching from the interrupted task stack to RTEMS software interrupt stack. |
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[b088292] | 66 | |
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| 67 | @section Default Fatal Error Processing |
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| 68 | |
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| 69 | The default fatal error handler for this architecture performs the |
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| 70 | following actions: |
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| 71 | |
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| 72 | @itemize @bullet |
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| 73 | @item disables operating system supported interrupts (IRQ), |
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| 74 | @item places the error code in @code{r0}, and |
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| 75 | @item executes an infinite loop to simulate a halt processor instruction. |
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| 76 | @end itemize |
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