1 | @c |
---|
2 | @c COPYRIGHT (c) 1988-2002. |
---|
3 | @c On-Line Applications Research Corporation (OAR). |
---|
4 | @c All rights reserved. |
---|
5 | |
---|
6 | @ifinfo |
---|
7 | @end ifinfo |
---|
8 | @chapter M68xxx and Coldfire Specific Information |
---|
9 | |
---|
10 | This chapter discusses the Freescale (formerly Motorola) MC68xxx |
---|
11 | and Coldfire architectural dependencies. The MC68xxx family has a |
---|
12 | wide variety of CPU models within it based upon different CPU core |
---|
13 | implementations. Ignoring the Coldfire parts, the part numbers for |
---|
14 | these models are generally divided into MC680xx and MC683xx. The MC680xx |
---|
15 | models are more general purpose processors with no integrated peripherals. |
---|
16 | The MC683xx models, on the other hand, are more specialized and have a |
---|
17 | variety of peripherals on chip including sophisticated timers and serial |
---|
18 | communications controllers. |
---|
19 | |
---|
20 | @subheading Architecture Documents |
---|
21 | |
---|
22 | For information on the MC68xxx and Coldfire architecture, refer to the following documents available from Freescale website (@file{http//www.freescale.com/}): |
---|
23 | |
---|
24 | @itemize @bullet |
---|
25 | @item @cite{M68000 Family Reference, Motorola, FR68K/D}. |
---|
26 | @item @cite{MC68020 User's Manual, Motorola, MC68020UM/AD}. |
---|
27 | @item @cite{MC68881/MC68882 Floating-Point Coprocessor User's Manual, |
---|
28 | Motorola, MC68881UM/AD}. |
---|
29 | @end itemize |
---|
30 | |
---|
31 | @c |
---|
32 | @c |
---|
33 | @c |
---|
34 | @section CPU Model Dependent Features |
---|
35 | |
---|
36 | |
---|
37 | This section presents the set of features which vary |
---|
38 | across m68k/Coldfire implementations that are of importance to RTEMS. |
---|
39 | The set of CPU model feature macros are defined in the file |
---|
40 | @code{cpukit/score/cpu/m68k/m68k.h} based upon the particular CPU |
---|
41 | model selected on the compilation command line. |
---|
42 | |
---|
43 | @subsection BFFFO Instruction |
---|
44 | |
---|
45 | The macro @code{M68K_HAS_BFFFO} is set to 1 to indicate that |
---|
46 | this CPU model has the bfffo instruction. |
---|
47 | |
---|
48 | @subsection Vector Base Register |
---|
49 | |
---|
50 | The macro @code{M68K_HAS_VBR} is set to 1 to indicate that |
---|
51 | this CPU model has a vector base register (vbr). |
---|
52 | |
---|
53 | @subsection Separate Stacks |
---|
54 | |
---|
55 | The macro @code{M68K_HAS_SEPARATE_STACKS} is set to 1 to |
---|
56 | indicate that this CPU model has separate interrupt, user, and |
---|
57 | supervisor mode stacks. |
---|
58 | |
---|
59 | @subsection Pre-Indexing Address Mode |
---|
60 | |
---|
61 | The macro @code{M68K_HAS_PREINDEXING} is set to 1 to indicate that |
---|
62 | this CPU model has the pre-indexing address mode. |
---|
63 | |
---|
64 | @subsection Extend Byte to Long Instruction |
---|
65 | |
---|
66 | The macro @code{M68K_HAS_EXTB_L} is set to 1 to indicate that this CPU model |
---|
67 | has the extb.l instruction. This instruction is supposed to be available |
---|
68 | in all models based on the cpu32 core as well as mc68020 and up models. |
---|
69 | |
---|
70 | @c |
---|
71 | @c |
---|
72 | @c |
---|
73 | @section Calling Conventions |
---|
74 | |
---|
75 | The MC68xxx architecture supports a simple yet effective call and |
---|
76 | return mechanism. A subroutine is invoked via the branch to subroutine |
---|
77 | (@code{bsr}) or the jump to subroutine (@code{jsr}) instructions. |
---|
78 | These instructions push the return address on the current stack. |
---|
79 | The return from subroutine (@code{rts}) instruction pops the return |
---|
80 | address off the current stack and transfers control to that instruction. |
---|
81 | It is is important to note that the MC68xxx call and return mechanism does |
---|
82 | not automatically save or restore any registers. It is the responsibility |
---|
83 | of the high-level language compiler to define the register preservation |
---|
84 | and usage convention. |
---|
85 | |
---|
86 | @subsection Calling Mechanism |
---|
87 | |
---|
88 | All RTEMS directives are invoked using either a @code{bsr} or @code{jsr} |
---|
89 | instruction and return to the user application via the rts instruction. |
---|
90 | |
---|
91 | @subsection Register Usage |
---|
92 | |
---|
93 | As discussed above, the @code{bsr} and @code{jsr} instructions do not |
---|
94 | automatically save any registers. RTEMS uses the registers D0, D1, |
---|
95 | A0, and A1 as scratch registers. These registers are not preserved by |
---|
96 | RTEMS directives therefore, the contents of these registers should not |
---|
97 | be assumed upon return from any RTEMS directive. |
---|
98 | |
---|
99 | @subsection Parameter Passing |
---|
100 | |
---|
101 | RTEMS assumes that arguments are placed on the current stack before |
---|
102 | the directive is invoked via the bsr or jsr instruction. The first |
---|
103 | argument is assumed to be closest to the return address on the stack. |
---|
104 | This means that the first argument of the C calling sequence is pushed |
---|
105 | last. The following pseudo-code illustrates the typical sequence used |
---|
106 | to call a RTEMS directive with three (3) arguments: |
---|
107 | |
---|
108 | @example |
---|
109 | @group |
---|
110 | push third argument |
---|
111 | push second argument |
---|
112 | push first argument |
---|
113 | invoke directive |
---|
114 | remove arguments from the stack |
---|
115 | @end group |
---|
116 | @end example |
---|
117 | |
---|
118 | The arguments to RTEMS are typically pushed onto the stack using a move |
---|
119 | instruction with a pre-decremented stack pointer as the destination. |
---|
120 | These arguments must be removed from the stack after control is returned |
---|
121 | to the caller. This removal is typically accomplished by adding the |
---|
122 | size of the argument list in bytes to the current stack pointer. |
---|
123 | |
---|
124 | @c |
---|
125 | @c |
---|
126 | @c |
---|
127 | @section Memory Model |
---|
128 | |
---|
129 | The MC68xxx family supports a flat 32-bit address |
---|
130 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
---|
131 | gigabytes). Each address is represented by a 32-bit value and |
---|
132 | is byte addressable. The address may be used to reference a |
---|
133 | single byte, word (2-bytes), or long word (4 bytes). Memory |
---|
134 | accesses within this address space are performed in big endian |
---|
135 | fashion by the processors in this family. |
---|
136 | |
---|
137 | Some of the MC68xxx family members such as the |
---|
138 | MC68020, MC68030, and MC68040 support virtual memory and |
---|
139 | segmentation. The MC68020 requires external hardware support |
---|
140 | such as the MC68851 Paged Memory Management Unit coprocessor |
---|
141 | which is typically used to perform address translations for |
---|
142 | these systems. RTEMS does not support virtual memory or |
---|
143 | segmentation on any of the MC68xxx family members. |
---|
144 | |
---|
145 | @c |
---|
146 | @c |
---|
147 | @c |
---|
148 | @section Interrupt Processing |
---|
149 | |
---|
150 | Discussed in this section are the MC68xxx's interrupt response and |
---|
151 | control mechanisms as they pertain to RTEMS. |
---|
152 | |
---|
153 | @subsection Vectoring of an Interrupt Handler |
---|
154 | |
---|
155 | Depending on whether or not the particular CPU supports a separate |
---|
156 | interrupt stack, the MC68xxx family has two different interrupt handling |
---|
157 | models. |
---|
158 | |
---|
159 | @subsubsection Models Without Separate Interrupt Stacks |
---|
160 | |
---|
161 | Upon receipt of an interrupt the MC68xxx family members without separate |
---|
162 | interrupt stacks automatically perform the following actions: |
---|
163 | |
---|
164 | @itemize @bullet |
---|
165 | @item To Be Written |
---|
166 | @end itemize |
---|
167 | |
---|
168 | @subsubsection Models With Separate Interrupt Stacks |
---|
169 | |
---|
170 | Upon receipt of an interrupt the MC68xxx family members with separate |
---|
171 | interrupt stacks automatically perform the following actions: |
---|
172 | |
---|
173 | @itemize @bullet |
---|
174 | @item saves the current status register (SR), |
---|
175 | |
---|
176 | @item clears the master/interrupt (M) bit of the SR to |
---|
177 | indicate the switch from master state to interrupt state, |
---|
178 | |
---|
179 | @item sets the privilege mode to supervisor, |
---|
180 | |
---|
181 | @item suppresses tracing, |
---|
182 | |
---|
183 | @item sets the interrupt mask level equal to the level of the |
---|
184 | interrupt being serviced, |
---|
185 | |
---|
186 | @item pushes an interrupt stack frame (ISF), which includes |
---|
187 | the program counter (PC), the status register (SR), and the |
---|
188 | format/exception vector offset (FVO) word, onto the supervisor |
---|
189 | and interrupt stacks, |
---|
190 | |
---|
191 | @item switches the current stack to the interrupt stack and |
---|
192 | vectors to an interrupt service routine (ISR). If the ISR was |
---|
193 | installed with the interrupt_catch directive, then the RTEMS |
---|
194 | interrupt handler will begin execution. The RTEMS interrupt |
---|
195 | handler saves all registers which are not preserved according to |
---|
196 | the calling conventions and invokes the application's ISR. |
---|
197 | @end itemize |
---|
198 | |
---|
199 | A nested interrupt is processed similarly by these |
---|
200 | CPU models with the exception that only a single ISF is placed |
---|
201 | on the interrupt stack and the current stack need not be |
---|
202 | switched. |
---|
203 | |
---|
204 | The FVO word in the Interrupt Stack Frame is examined |
---|
205 | by RTEMS to determine when an outer most interrupt is being |
---|
206 | exited. Since the FVO is used by RTEMS for this purpose, the |
---|
207 | user application code MUST NOT modify this field. |
---|
208 | |
---|
209 | The following shows the Interrupt Stack Frame for |
---|
210 | MC68xxx CPU models with separate interrupt stacks: |
---|
211 | |
---|
212 | @ifset use-ascii |
---|
213 | @example |
---|
214 | @group |
---|
215 | +----------------------+ |
---|
216 | | Status Register | 0x0 |
---|
217 | +----------------------+ |
---|
218 | | Program Counter High | 0x2 |
---|
219 | +----------------------+ |
---|
220 | | Program Counter Low | 0x4 |
---|
221 | +----------------------+ |
---|
222 | | Format/Vector Offset | 0x6 |
---|
223 | +----------------------+ |
---|
224 | @end group |
---|
225 | @end example |
---|
226 | @end ifset |
---|
227 | |
---|
228 | @ifset use-tex |
---|
229 | @sp 1 |
---|
230 | @tex |
---|
231 | \centerline{\vbox{\offinterlineskip\halign{ |
---|
232 | \strut\vrule#& |
---|
233 | \hbox to 2.00in{\enskip\hfil#\hfil}& |
---|
234 | \vrule#& |
---|
235 | \hbox to 0.50in{\enskip\hfil#\hfil} |
---|
236 | \cr |
---|
237 | \multispan{3}\hrulefill\cr |
---|
238 | & Status Register && 0x0\cr |
---|
239 | \multispan{3}\hrulefill\cr |
---|
240 | & Program Counter High && 0x2\cr |
---|
241 | \multispan{3}\hrulefill\cr |
---|
242 | & Program Counter Low && 0x4\cr |
---|
243 | \multispan{3}\hrulefill\cr |
---|
244 | & Format/Vector Offset && 0x6\cr |
---|
245 | \multispan{3}\hrulefill\cr |
---|
246 | }}\hfil} |
---|
247 | @end tex |
---|
248 | @end ifset |
---|
249 | |
---|
250 | @ifset use-html |
---|
251 | @html |
---|
252 | <CENTER> |
---|
253 | <TABLE COLS=2 WIDTH="40%" BORDER=2> |
---|
254 | <TR><TD ALIGN=center><STRONG>Status Register</STRONG></TD> |
---|
255 | <TD ALIGN=center>0x0</TD></TR> |
---|
256 | <TR><TD ALIGN=center><STRONG>Program Counter High</STRONG></TD> |
---|
257 | <TD ALIGN=center>0x2</TD></TR> |
---|
258 | <TR><TD ALIGN=center><STRONG>Program Counter Low</STRONG></TD> |
---|
259 | <TD ALIGN=center>0x4</TD></TR> |
---|
260 | <TR><TD ALIGN=center><STRONG>Format/Vector Offset</STRONG></TD> |
---|
261 | <TD ALIGN=center>0x6</TD></TR> |
---|
262 | </TABLE> |
---|
263 | </CENTER> |
---|
264 | @end html |
---|
265 | @end ifset |
---|
266 | |
---|
267 | @subsection CPU Models Without VBR and RAM at 0 |
---|
268 | |
---|
269 | This is from a post by Zoltan Kocsi <zoltan@@bendor.com.au> and is |
---|
270 | a nice trick in certain situations. In his words: |
---|
271 | |
---|
272 | I think somebody on this list asked about the interupt vector handling |
---|
273 | w/o VBR and RAM at 0. The usual trick is to initialise the vector table |
---|
274 | (except the first 2 two entries, of course) to point to the same location |
---|
275 | BUT you also add the vector number times 0x1000000 to them. That is, |
---|
276 | bits 31-24 contain the vector number and 23-0 the address of the common |
---|
277 | handler. Since the PC is 32 bit wide but the actual address bus is only |
---|
278 | 24, the top byte will be in the PC but will be ignored when jumping onto |
---|
279 | your routine. |
---|
280 | |
---|
281 | Then your common interrupt routine gets this info by loading the PC |
---|
282 | into some register and based on that info, you can jump to a vector in |
---|
283 | a vector table pointed by a virtual VBR: |
---|
284 | |
---|
285 | @example |
---|
286 | // |
---|
287 | // Real vector table at 0 |
---|
288 | // |
---|
289 | |
---|
290 | .long initial_sp |
---|
291 | .long initial_pc |
---|
292 | .long myhandler+0x02000000 |
---|
293 | .long myhandler+0x03000000 |
---|
294 | .long myhandler+0x04000000 |
---|
295 | ... |
---|
296 | .long myhandler+0xff000000 |
---|
297 | |
---|
298 | |
---|
299 | // |
---|
300 | // This handler will jump to the interrupt routine of which |
---|
301 | // the address is stored at VBR[ vector_no ] |
---|
302 | // The registers and stackframe will be intact, the interrupt |
---|
303 | // routine will see exactly what it would see if it was called |
---|
304 | // directly from the HW vector table at 0. |
---|
305 | // |
---|
306 | |
---|
307 | .comm VBR,4,2 // This defines the 'virtual' VBR |
---|
308 | // From C: extern void *VBR; |
---|
309 | |
---|
310 | myhandler: // At entry, PC contains the full vector |
---|
311 | move.l %d0,-(%sp) // Save d0 |
---|
312 | move.l %a0,-(%sp) // Save a0 |
---|
313 | lea 0(%pc),%a0 // Get the value of the PC |
---|
314 | move.l %a0,%d0 // Copy it to a data reg, d0 is VV?????? |
---|
315 | swap %d0 // Now d0 is ????VV?? |
---|
316 | and.w #0xff00,%d0 // Now d0 is ????VV00 (1) |
---|
317 | lsr.w #6,%d0 // Now d0.w contains the VBR table offset |
---|
318 | move.l VBR,%a0 // Get the address from VBR to a0 |
---|
319 | move.l (%a0,%d0.w),%a0 // Fetch the vector |
---|
320 | move.l 4(%sp),%d0 // Restore d0 |
---|
321 | move.l %a0,4(%sp) // Place target address to the stack |
---|
322 | move.l (%sp)+,%a0 // Restore a0, target address is on TOS |
---|
323 | ret // This will jump to the handler and |
---|
324 | // restore the stack |
---|
325 | |
---|
326 | (1) If 'myhandler' is guaranteed to be in the first 64K, e.g. just |
---|
327 | after the vector table then that insn is not needed. |
---|
328 | |
---|
329 | @end example |
---|
330 | |
---|
331 | There are probably shorter ways to do this, but it I believe is enough |
---|
332 | to illustrate the trick. Optimisation is left as an exercise to the |
---|
333 | reader :-) |
---|
334 | |
---|
335 | |
---|
336 | @subsection Interrupt Levels |
---|
337 | |
---|
338 | Eight levels (0-7) of interrupt priorities are |
---|
339 | supported by MC68xxx family members with level seven (7) being |
---|
340 | the highest priority. Level zero (0) indicates that interrupts |
---|
341 | are fully enabled. Interrupt requests for interrupts with |
---|
342 | priorities less than or equal to the current interrupt mask |
---|
343 | level are ignored. |
---|
344 | |
---|
345 | Although RTEMS supports 256 interrupt levels, the |
---|
346 | MC68xxx family only supports eight. RTEMS interrupt levels 0 |
---|
347 | through 7 directly correspond to MC68xxx interrupt levels. All |
---|
348 | other RTEMS interrupt levels are undefined and their behavior is |
---|
349 | unpredictable. |
---|
350 | |
---|
351 | @c |
---|
352 | @c |
---|
353 | @c |
---|
354 | @section Default Fatal Error Processing |
---|
355 | |
---|
356 | The default fatal error handler for this architecture disables processor |
---|
357 | interrupts to level 7, places the error code in D0, and executes a |
---|
358 | @code{stop} instruction to simulate a halt processor instruction. |
---|
359 | |
---|
360 | @c |
---|
361 | @c |
---|
362 | @c |
---|
363 | |
---|
364 | @section Board Support Packages |
---|
365 | |
---|
366 | @subsection System Reset |
---|
367 | |
---|
368 | An RTEMS based application is initiated or re-initiated when the MC68020 |
---|
369 | processor is reset. When the MC68020 is reset, the processor performs |
---|
370 | the following actions: |
---|
371 | |
---|
372 | @itemize @bullet |
---|
373 | @item The tracing bits of the status register are cleared to |
---|
374 | disable tracing. |
---|
375 | |
---|
376 | @item The supervisor interrupt state is entered by setting the |
---|
377 | supervisor (S) bit and clearing the master/interrupt (M) bit of |
---|
378 | the status register. |
---|
379 | |
---|
380 | @item The interrupt mask of the status register is set to |
---|
381 | level 7 to effectively disable all maskable interrupts. |
---|
382 | |
---|
383 | @item The vector base register (VBR) is set to zero. |
---|
384 | |
---|
385 | @item The cache control register (CACR) is set to zero to |
---|
386 | disable and freeze the processor cache. |
---|
387 | |
---|
388 | @item The interrupt stack pointer (ISP) is set to the value |
---|
389 | stored at vector 0 (bytes 0-3) of the exception vector table |
---|
390 | (EVT). |
---|
391 | |
---|
392 | @item The program counter (PC) is set to the value stored at |
---|
393 | vector 1 (bytes 4-7) of the EVT. |
---|
394 | |
---|
395 | @item The processor begins execution at the address stored in |
---|
396 | the PC. |
---|
397 | @end itemize |
---|
398 | |
---|
399 | @subsection Processor Initialization |
---|
400 | |
---|
401 | The address of the application's initialization code should be stored in |
---|
402 | the first vector of the EVT which will allow the immediate vectoring to |
---|
403 | the application code. If the application requires that the VBR be some |
---|
404 | value besides zero, then it should be set to the required value at this |
---|
405 | point. All tasks share the same MC68020's VBR value. Because interrupts |
---|
406 | are enabled automatically by RTEMS as part of the context switch to the |
---|
407 | first task, the VBR MUST be set by either RTEMS of the BSP before this |
---|
408 | occurs ensure correct interrupt vectoring. If processor caching is |
---|
409 | to be utilized, then it should be enabled during the reset application |
---|
410 | initialization code. |
---|
411 | |
---|
412 | In addition to the requirements described in the |
---|
413 | Board Support Packages chapter of the Applications User's |
---|
414 | Manual for the reset code which is executed before the call to |
---|
415 | initialize executive, the MC68020 version has the following |
---|
416 | specific requirements: |
---|
417 | |
---|
418 | @itemize @bullet |
---|
419 | @item Must leave the S bit of the status register set so that |
---|
420 | the MC68020 remains in the supervisor state. |
---|
421 | |
---|
422 | @item Must set the M bit of the status register to remove the |
---|
423 | MC68020 from the interrupt state. |
---|
424 | |
---|
425 | @item Must set the master stack pointer (MSP) such that a |
---|
426 | minimum stack size of MINIMUM_STACK_SIZE bytes is provided for |
---|
427 | the initialize executive directive. |
---|
428 | |
---|
429 | @item Must initialize the MC68020's vector table. |
---|
430 | @end itemize |
---|
431 | |
---|