1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, |
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6 | @c Micro-Research Finland Oy |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @end ifinfo |
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11 | @chapter Lattice Mico32 Specific Information |
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12 | |
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13 | This chaper discusses the Lattice Mico32 architecture dependencies in |
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14 | this port of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC |
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15 | architecture "soft" microprocessor, available for free with an open IP |
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16 | core licensing agreement. Although mainly targeted for Lattice FPGA |
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17 | devices the microprocessor can be implemented on other vendors' FPGAs, |
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18 | too. |
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19 | |
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20 | @subheading Architecture Documents |
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21 | |
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22 | For information on the Lattice Mico32 architecture, refer to the |
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23 | following documents available from Lattice Semiconductor |
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24 | @file{http://www.latticesemi.com/}. |
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25 | |
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26 | @itemize @bullet |
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27 | @item @cite{"LatticeMico32 Processor Reference Manual"} |
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28 | @file{http://www.latticesemi.com/dynamic/view_document.cfm?document_id=20890} |
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29 | @end itemize |
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30 | |
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31 | @c |
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32 | @c |
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33 | @c |
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34 | @section CPU Model Dependent Features |
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35 | |
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36 | The Lattice Mico32 architecture allows for different configurations of |
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37 | the processor. This port is based on the assumption that the following options are implemented: |
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38 | |
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39 | @itemize @bullet |
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40 | @item hardware multiplier |
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41 | @item hardware divider |
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42 | @item hardware barrel shifter |
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43 | @item sign extension instructions |
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44 | @item instruction cache |
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45 | @item data cache |
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46 | @item debug |
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47 | @end itemize |
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48 | |
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49 | @c |
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50 | @c |
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51 | @c |
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52 | @section Register Architecture |
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53 | |
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54 | This section gives a brief introduction to the register architecture |
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55 | of the Lattice Mico32 processor. |
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56 | |
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57 | The Lattice Mico32 is a RISC archictecture processor with a |
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58 | 32-register file of 32-bit registers. |
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59 | |
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60 | @multitable {Register Name} {general pupose / global pointer} |
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61 | @headitem Register Name @tab Function |
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62 | @item r0 @tab holds value zero |
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63 | @item r1-r25 @tab general purpose |
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64 | @item r26/gp @tab general pupose / global pointer |
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65 | @item r27/fp @tab general pupose / frame pointer |
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66 | @item r28/sp @tab stack pointer |
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67 | @item r29/ra @tab return address |
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68 | @item r30/ea @tab exception address |
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69 | @item r31/ba @tab breakpoint address |
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70 | @end multitable |
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71 | |
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72 | Note that on processor startup all register values are undefined |
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73 | including r0, thus r0 has to be initialized to zero. |
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74 | |
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75 | @c |
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76 | @c |
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77 | @c |
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78 | @section Calling Conventions |
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79 | |
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80 | @subsection Calling Mechanism |
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81 | |
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82 | A call instruction places the return address to register r29 and a |
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83 | return from subroutine (ret) is actually a branch to r29/ra. |
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84 | |
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85 | @subsection Register Usage |
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86 | |
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87 | A subroutine may freely use registers r1 to r10 which are @b{not} |
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88 | preserved across subroutine invocations. |
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89 | |
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90 | @subsection Parameter Passing |
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91 | |
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92 | When calling a C function the first eight arguments are stored in |
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93 | registers r1 to r8. Registers r1 and r2 hold the return value. |
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94 | |
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95 | @c |
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96 | @c |
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97 | @c |
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98 | @section Memory Model |
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99 | |
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100 | The Lattice Mico32 processor supports a flat memory model with a 4 |
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101 | Gbyte address space with 32-bit addresses. |
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102 | |
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103 | The following data types are supported: |
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104 | |
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105 | @multitable {unsigned half-word} {Bits} {unsigned int / unsigned long} |
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106 | @headitem Type @tab Bits @tab C Compiler Type |
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107 | @item unsigned byte @tab 8 @tab unsigned char |
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108 | @item signed byte @tab 8 @tab char |
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109 | @item unsigned half-word @tab 16 @tab unsigned short |
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110 | @item signed half-word @tab 16 @tab short |
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111 | @item unsigned word @tab 32 @tab unsigned int / unsigned long |
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112 | @item signed word @tab 32 @tab int / long |
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113 | @end multitable |
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114 | |
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115 | Data accesses need to be aligned, with unaligned accesses result are |
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116 | undefined. |
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117 | |
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118 | @c |
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119 | @c |
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120 | @c |
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121 | @section Interrupt Processing |
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122 | |
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123 | The Lattice Mico32 has 32 interrupt lines which are however served by |
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124 | only one exception vector. When an interrupt occurs following happens: |
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125 | |
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126 | @itemize @bullet |
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127 | @item address of next instruction placed in r30/ea |
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128 | @item IE field of IE CSR saved to EIE field and IE field cleared preventing further exceptions from occuring. |
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129 | @item branch to interrupt exception address EBA CSR + 0xC0 |
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130 | @end itemize |
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131 | |
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132 | The interrupt exception handler determines from the state of the |
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133 | interrupt pending registers (IP CSR) and interrupt enable register (IE |
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134 | CSR) which interrupt to serve and jumps to the interrupt routine |
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135 | pointed to by the corresponding interrupt vector. |
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136 | |
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137 | For now there is no dedicated interrupt stack so every task in |
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138 | the system MUST have enough stack space to accommodate the worst |
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139 | case stack usage of that particular task and the interrupt |
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140 | service routines COMBINED. |
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141 | |
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142 | Nested interrupts are not supported. |
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143 | |
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144 | @c |
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145 | @c |
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146 | @c |
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147 | @section Default Fatal Error Processing |
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148 | |
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149 | Upon detection of a fatal error by either the application or RTEMS during |
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150 | initialization the @code{rtems_fatal_error_occurred} directive supplied |
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151 | by the Fatal Error Manager is invoked. The Fatal Error Manager will |
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152 | invoke the user-supplied fatal error handlers. If no user-supplied |
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153 | handlers are configured or all of them return without taking action to |
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154 | shutdown the processor or reset, a default fatal error handler is invoked. |
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155 | |
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156 | Most of the action performed as part of processing the fatal error are |
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157 | described in detail in the Fatal Error Manager chapter in the User's |
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158 | Guide. However, the if no user provided extension or BSP specific fatal |
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159 | error handler takes action, the final default action is to invoke a |
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160 | CPU architecture specific function. Typically this function disables |
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161 | interrupts and halts the processor. |
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162 | |
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163 | In each of the architecture specific chapters, this describes the precise |
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164 | operations of the default CPU specific fatal error handler. |
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165 | |
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166 | @c |
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167 | @c |
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168 | @c |
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169 | |
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170 | @section Board Support Packages |
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171 | |
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172 | An RTEMS Board Support Package (BSP) must be designed to support a |
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173 | particular processor model and target board combination. |
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174 | |
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175 | In each of the architecture specific chapters, this section will present |
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176 | a discussion of architecture specific BSP issues. For more information |
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177 | on developing a BSP, refer to BSP and Device Driver Development Guide |
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178 | and the chapter titled Board Support Packages in the RTEMS |
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179 | Applications User's Guide. |
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180 | |
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181 | @subsection System Reset |
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182 | |
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183 | An RTEMS based application is initiated or re-initiated when the processor |
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184 | is reset. |
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